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HV testing:


Baseline configuration:

Top and Bottom wire-bonded

No pinholes found (by looking for channels with anomalously low noise)

NO Bias

80V Bias

icalScan Analysis:

(Pulses missing due to error in script. To fix: Change csel setting from 0 → 1 in icalScanAnalysis.py)

Will repeat this test and update (06/16/2021 A.S.)

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