Meeting with Yves Acremann and Matt Weaver and representative from Surface Concept on May 27, 2021.
surface concept dld
dld (delay line detector) with yves acremann
timing interface board: matt's timing signal with LVDS output to DLD.
- like camlink converter but needs timing input interface
- triger TTL output <40ps jitter from "tprtrig"?
- triggering: 3.3V TTL
who is involved?
- slac: zx shen
- germany
- lcls: bob schoenlein (georgi)
schedule?
- start in spring 2022 in NEH2.2
monitoring
- we'll try ami and/or psana-python from shared memory
language of monitoring software?
- low level c++
- higher level python
data aggregated before daq node with switch going to ONE 10Gbit ethernet
data path: ethernet into one daq node
need deadtime
interface to DAQ (between surface-concept driver receiving UDP (ack'd) and DAQ)
two callbacks:
- a block of each electron has x,y,t, and lower-bits of pulse id
- are electrons in pulse-id-order? if not resorting could be a problem @1MHz
- they don't expect many electrons per pulse (10?)
- bytes per electron: 64-bit, 2 bytes x,y, t is 3 bytes, and lower-bits of pulse-id (80MB/s at 1MHz). number of bits are fixed, but can be changed in hardware if necessary.
- full timestamp (for upper bits) once per ms
could maybe ship a tdc plus pulse generator to simulate electrons earlier to slac.
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