Current Development Machine Name
lcls-pc83236
Preparing git ssh keys
Add your ssh keys to git (This is unfortunately necessary because the .gitmodules file in lcls2-pcie-apps uses the "git" form of the URL instead of the "http" form):
https://help.github.com/articles/adding-a-new-ssh-key-to-your-github-account/
Also note that the firmware requires a new version of git that supports "links to large files" (lfs). Add /afs/slac/g/reseng/git/git/bin to PATH.
Conda Commands to Create Rogue Environment
This is in addition to the other packages that must be built for the rogue library (see next step). These conda commands are derived from:
https://github.com/slaclab/rogue/blob/master/Readme_python3.txt
conda env create -n timetool source activate timetool conda install pyyaml conda install pyzmq conda install -c conda-forge parse conda install click conda install MySQLdb conda install -c bioconda mysqlclient conda install -c conda-forge pyro4 conda install numpy pip install recordclass
Building Rogue
git clone https://github.com/slaclab/rogue.git
Needs a conda env with a bunch of stuff (previous step). Follow build instruction files in the rogue root directory README files (although I suggest setting up a conda python3 env (previous step) instead of using pip install):
https://github.com/slaclab/rogue/blob/master/Readme_build.txt
cd rogue
git submodule init
git submodule update
make
To run, source this script:
https://github.com/slaclab/lcls2-pcie-apps/blob/master/software/TimeTool/setup_env_template.csh
Some applications are not built by default. cd to directory and make.
Building Firmware
Follow instructions in the README.md here (make sure to use the modern AFS version of git described here so you can use git-lfs):
https://github.com/slaclab/lcls2-pcie-apps.git
git submodule init
git submodule update
(old: source /afs/slac/g/reseng/xilinx/vivado_2017.3/Vivado/2017.3/settings64.sh #this isn't working on 1/31/2018. sourcing below instead)
source lcls2-pcie-apps/firmware/setup_env_slac.sh
if you want to store the output of "make" on your local machine: in the "firmware/" directory, "ln -s /u1/sioan/build ."
cd firmware/targets/TimeToolKcu1500
make
Making Vivado communicate with board over USB/JTAG
Larry has some slides on how to program the flash chips (mt25qu512) on the KCU1500 via USB/JTAG. Startup "vivado" after setting up the firmware
Do this to program with flash chips on the KCU1500 for the first time. Before programming lspci will show:
02:00.0 Serial controller: Xilinx Corporation Device 8638 (rev ff)
After programming powercycle the machine. Then lspci should show:
02:00.0 Signal processing controller: SLAC National Accelerator Lab PPA-REG Device 2030
#https://www.xilinx.com/support/answers/59128.html
1) Disconnect all Xilinx USB cables from the host computer.
2) Open a shell or terminal console.
3) Extract the driver script and its support files to a local drive of the machine where the cable will be used by typing:
#must cd to directory. Can't run install_drivers from arbitrary directory.
cd /afs/slac.stanford.edu/g/reseng/xilinx/vivado_2017.4/Vivado/2017.4/data/xicom/cable_drivers/lin64/install_script/install_drivers/
sudo ./install_drivers
#now vivado hardware manager will see the kcu1500 board.
#instructions to program using vivado hardware manager in link below
SLAC Driver
Build/install the datadev.ko driver using the instructions here:
https://github.com/slaclab/lcls2-pcie-apps
This needs to be done on the machine where the KCU1500 lives. You need sudo on the machine to install the driver.
Programming FPGA over PCI
After the first programming (and power-cycling) described above, use this script to reprogram:
https://github.com/slaclab/lcls2-pcie-apps/blob/master/software/TimeTool/scripts/updateProm.py
TimeTool Software Files
lcls2-pcie-apps/firmware/applications/TimeTool/python/TimeTool.py: a description of the "addValue" register
lcls2-pcie-apps/firmware/submodules/surf/python/surf/protocols/clink/*.py: descriptions of the "clink" (cameralink) parameters
lcls2-pcie-apps/software/TimeTool/python/TimeToolDev.py: top level class called by gui.py. opens /dev/datadev_0, glues together various register maps using classes like ClinkTest, TimeToolCore, dataWriter
In TimeToolDev.py:
- self.add adds registers and associated GUI control
Settings Needed To Run Camera
Use channela:
- send escape right away after powering up
- datamode: using medium 8bit
- framemode: our camera only gives a line valid (indication that there is valid data) so we need to set to "line"
- tapcount: our camera sends 4 bytes where it could send 6
- dataen: enables the data block (leave false until able to receive data)
- baudrate: 9600
- use sendGCP to test serial link is working (output should appear on terminal)
- swcontrolvalue/swcontrolen: bits for hardware vs software trigger (0/0 internal trigger)
- running: status bit (am I getting frames from camera)
- dropcount: 3 channels misaligned (errors)
- have to set both sender/receiver to "medium". send these TLC strings to the camera:
- CLM 1 (cameralink medium mode)
- SVM 1 (test pattern ramp)
- SSF 1 (software trigger rate 1Hz, although seems to read back as 6Hz? and 2 reads back as 12Hz?)
Camera output should appear on terminal after setting ClinkTop->ChannelA->DataEn to True
Output of SendGCP:
Got Response: Got Response: Model P4_CM_02K10D_00_R Got Response: Microcode 03-081-20296-13 Got Response: CCI 03-110-20294-03 Got Response: FPGA 03-056-20470-03 Got Response: Serial # 12102856 Got Response: BiST: Good Got Response: Got Response: DefaultSet 1 Got Response: Ext Trig Off Got Response: Trig Overlap Off Got Response: Line Rate 1 [Hz] Got Response: Meas L.R. 6 [Hz] Got Response: Max L.R. 19607 [Hz] Got Response: Exp. Mode Timed Got Response: Multi Exp. Mode Off Got Response: Exp. Time[0] 50000 [ns] Got Response: Meas E.T.[0] 50000 [ns] Got Response: Max E.T. 3000500 [ns] Got Response: Got Response: Test Pat. 1:Ramp1 Got Response: Direction Internal, Forward Got Response: TDI Stages 2 Got Response: Vert. Bin 1 Got Response: Hor. Bin 1 Got Response: Flat Field Off Got Response: Offset 0 Got Response: System Gain 1.00 Got Response: Mirror Off Got Response: AOI Mode: Off Got Response: Scan Type Line Scan Got Response: CL Speed 85MHz Got Response: CL Config Medium Got Response: Pixel Fmt 8 bits Got Response: CPA ROI 1-2048