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Requirements

  1. Two D-Port connections to the front end board (FEB)
  2. Support both GT or I/O interface to (FEB)
    1. Requires fanout ICs and MUXs
    2. I/O for low speed serial
    3. GT for high speed serial
  3. Support 8x GT for Back End Board (BEB) and FEB
    1. 4x for FEB on D-Port Connector
    2. 4x for BEB on 4x SFP+ cages
  4. GT support up to 6.6 Gbps
    1. Optionally 10 Gbps with more expensive FPGA
  5. Support ATLAS timing
    1. SFP cage (same as CHESS2 board)
    2. Includes CDR IC
  6. Support Jitter Cleaner IC for GBT communication
  7. Some BNC connectors for TTL IN and TTL OUT
  8. Diff. LEMO connector for external clock
  9. +12VDC Power

 

 

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