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Daughter Board Requirements:

  • Board + cables needs to fit within a ??? x ??? x ??? box
  • Board Material:
    • FR4
    • same as CHESS1
  • Board Thickness:  
    • standard 1.6mm thickness
    • same as CHESS1 
  • Allow board components:
    • ASIC, resistors, capacitor, wire bonds, HV LEMO
  • ASIC-to-board epoxy material:  
    • ???
  • Resistor Type:
    • Thin film only
  • Capacitor Type:
    • Ceramics only
  • Wire bonds Material:
    • ???
  • ASIC Thermal Management Plan:  
    • ???
  • HV LEMO:
    • Standard LEMO
    • But positioned as far as possible from the ASIC
  • Board Connector:
    • Gold finger edge connector???
  • Able to test the daughter board before and after radiation without unsoldering/soldering any component:
    • Achieved via the edge connector
  • Convenient HV and LV powering scheme:
    • HV through LEMO
    • LV through daughter-to-carrier cabling
  • Only implement the high speed digital signals???
    • Off load the test structure testing to the CHESS1 carrier board???
    • Requires a different CHESS2 daughter card design for CHESS1 board???

Carrier Board Requirements:

  • Support full 3+1, Pair only, 1+Test chip configurations
  • Detachable passive daughter card for irradiation
  • Flexible connection scheme to support edge TCT, test beam setups (in particular cold daughter board regime)
  • Flexible timing control for multi-chip operation
  • Interface to backend readout with just one SFP fiber link should be the most flexible generic form for evolution.     

  • Ideally, also allow easy extension to ABCN’, HCC* and GBT emulation.   

  • Generic control/data interface for compatibility with main backend readout schemes of RCE and NEXYS video
    • RCE via SFP
    • NEXY via SFP (and FMC???)

 

 

 

 

 

 

 

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