Presentations
Summary Table:
Green Fileed = Supported
Red Filled = Not Supported
| 2014.1 | 2014.2 | 2014.3 | 2014.4 | 2015.1 | 2015.2 | 2015.3 | 2015.4 | 2016.1 | |
|---|---|---|---|---|---|---|---|---|---|
| Multiple IP core generation (including ZYNQ IP core) |
| TBD | |||||||
| PROM generation | |||||||||
| ILA Debug generation | TBD | ||||||||
| VCS script generation via Vivado platform | TBD | ||||||||
| Incremental Compile | |||||||||
| Partial Configuration | TBD | ||||||||
| Vivado HLS | |||||||||
| System Generator | TBD |
Note: We are not supporting any Vivado version before 2014.1
Note: Xilinx has dropped 32-bit support for version 2015.1 (or later). If you are building on a 32-bit Linux kernel, you will need to use 2014.4 (or earlier).
Note: We are only supporting "Incremental Compile" for version 2015.3 (or later) <http://www.xilinx.com/video/hardware/incremental-compile-updates-for-2015_3.html>
Vivado HLS
- We don't support Vivado HLS for version 2014.2 because requires too many manual soft-links to be created for the library paths to make it work.
System Generator
- Due to AR# 59236, we are not supporting System Generator before 2014.3
- For 2015.3, there is a bug in System Generator exporting both RTL and .DCP. In both exporting types, System Generator hangs and never generates the output files. This was tested using both Matlab R2014b and R2015b
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