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Presentations

Summary Table

 2014.12014.22014.32014.42015.12015.22015.32015.4
Multiple IP core generation (including ZYNQ IP core)








TBD

PROM generation       TBD
ILA Debug generation       TBD
VCS script generation via Vivado platform       TBD
Partial Configuration       TBD
Vivado HLS       TBD
System Generator       TBD

Note: We are not supporting any Vivado version before 2014.1

Note: Xilinx has dropped 32-bit support for version 2015.1 (or later).  If you are building on a 32-bit Linux kernel, you will need to use 2014.4 (or earlier).

Vivado HLS

  • We don't support Vivado HLS for version 2014.2 because requires too many manual soft-links to be created for the library paths to make it work.

System Generator

  • Due to AR# 59236, we are not supporting System Generator before 2014.3
  • For 2015.3, there is a bug in System Generator exporting both RTL and .DCP.  In both exporting types, System Generator hangs and never generates the output files.  This was tested using both Matlab R2014b and R2015b

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