The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
The FPGA has two types of GT quads:
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
From FPGA to PC:
Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and purple/blue):
This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview above for more details on the system clock structure.
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s"
Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | |
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C | ||||||||
Clock | |← | ← X → | →| | | X → | →| | | X → | →| | |||||||||||||||
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | ||
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
There is one GTY quad and one GTH quad left over.
← ePixUHR35kHz - Megapixel Cameras
The FPGA that will be used is XCKU15P-2FFVA1760E from AMD/Xilinx.
12V vs 24V (GT readout platform) vs 48V (TXI) input?
Is external electrical timing needed?
How many ADC channels are needed?
Do we need a high-speed ADC?
NHQM103B375T10 10k NTC type thermistors are used at:
One HIH-5031-001 sensor mounted close to the carrier connector.
A DS2411R+T&R chip is located on the readout board to provide a unique ID that can be read out by the FPGA. Another ID chip is also place on the carrier board.
Used to store the FPGA configuration.
Used to store operational settings and parameters.
A 14-pin JTAG connector (Molex 87832-1420) is located at the bottom of the readout board to not interfere with the cold plate on the top.
Option A Same components as used in the GT readout platform | Option B New components with PMBUS capability |
---|---|
|
https://www.xilinx.com/products/technology/power/xpe.html
From ASIC to FPGA:
Analog | Digital and I/O | Analog test system | |
---|---|---|---|
Net | G_AS | G_DS | G_AS_2V5 |
Voltage | 1.3 V | 1.3V | 2.5 V |
Required current per ASIC | 1.85 A ≈ 1.9 A | 0.468 A ≈ 0.5 A | 0.01 A |
System requirement with 6 ASICs (adding +30% current for PVT variation) | 6*1.9*1.3=14.82 A +1.3 V @ 15 A 1.3*15=19.5 W | 6*0.5*1.3=3.9 A +1.3 V @ 4.0 A 1.3*4=5.2 W | 6*0.01*1.3=0.078 A +2.5 V @ 0.5 A 2.5*0.5=1.25 W |
TODO
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
The FPGA has two types of GT quads:
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
From FPGA to PC:
Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and purple/blue):
This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview above for more details on the system clock structure.
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s"
Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | |
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C | ||||||||
Clock | |← | ← X → | →| | | X → | →| | | X → | →| | |||||||||||||||
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | ||
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
There is one GTY quad and one GTH quad left over.
← ePixUHR35kHz - Megapixel Cameras
The FPGA that will be used is XCKU15P-2FFVA1760E from AMD/Xilinx.
12V vs 24V (GT readout platform) vs 48V (TXI) input?
Is external electrical timing needed?
How many ADC channels are needed?
Do we need a high-speed ADC?
NHQM103B375T10 10k NTC type thermistors are used at:
One HIH-5031-001 sensor mounted close to the carrier connector.
A DS2411R+T&R chip is located on the readout board to provide a unique ID that can be read out by the FPGA. Another ID chip is also place on the carrier board.
Used to store the FPGA configuration.
Used to store operational settings and parameters.
A 14-pin JTAG connector (Molex 87832-1420) is located at the bottom of the readout board to not interfere with the cold plate on the top.
Option A Same components as used in the GT readout platform | Option B New components with PMBUS capability |
---|---|
|
|
https://www.xilinx.com/products/technology/power/xpe.html
From ASIC to FPGA:
Analog | Digital and I/O | Analog test system | |
---|---|---|---|
Net | G_AS | G_DS | G_AS_2V5 |
Voltage | 1.3 V | 1.3V | 2.5 V |
Required current per ASIC | 1.85 A ≈ 1.9 A | 0.468 A ≈ 0.5 A | 0.01 A |
System requirement with 6 ASICs (adding +30% current for PVT variation) | 6*1.9*1.3=14.82 A +1.3 V @ 15 A 1.3*15=19.5 W | 6*0.5*1.3=3.9 A +1.3 V @ 4.0 A 1.3*4=5.2 W | 6*0.01*1.3=0.078 A +2.5 V @ 0.5 A 2.5*0.5=1.25 W |
TODO
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
The FPGA has two types of GT quads:
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
From FPGA to PC:
Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and purple/blue):
This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview above for more details on the system clock structure.
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s"
Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | |
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C | ||||||||
Clock | |← | ← X → | →| | | X → | →| | | X → | →| | |||||||||||||||
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | ||
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
There is one GTY quad and one GTH quad left over.
← ePixUHR35kHz - Megapixel Cameras
The FPGA that will be used is XCKU15P-2FFVA1760E from AMD/Xilinx.
12V vs 24V (GT readout platform) vs 48V (TXI) input?
Is external electrical timing needed?
How many ADC channels are needed?
Do we need a high-speed ADC?
NHQM103B375T10 10k NTC type thermistors are used at:
One HIH-5031-001 sensor mounted close to the carrier connector.
A DS2411R+T&R chip is located on the readout board to provide a unique ID that can be read out by the FPGA. Another ID chip is also place on the carrier board.
Used to store the FPGA configuration.
Used to store operational settings and parameters.
A 14-pin JTAG connector (Molex 87832-1420) is located at the bottom of the readout board to not interfere with the cold plate on the top.
Option A Same components as used in the GT readout platform | Option B New components with PMBUS capability |
---|---|
|
https://www.xilinx.com/products/technology/power/xpe.html
From ASIC to FPGA:
Analog | Digital and I/O | Analog test system | |
---|---|---|---|
Net | G_AS | G_DS | G_AS_2V5 |
Voltage | 1.3 V | 1.3V | 2.5 V |
Required current per ASIC | 1.85 A ≈ 1.9 A | 0.468 A ≈ 0.5 A | 0.01 A |
System requirement with 6 ASICs (adding +30% current for PVT variation) | 6*1.9*1.3=14.82 A +1.3 V @ 15 A 1.3*15=19.5 W | 6*0.5*1.3=3.9 A +1.3 V @ 4.0 A 1.3*4=5.2 W | 6*0.01*1.3=0.078 A +2.5 V @ 0.5 A 2.5*0.5=1.25 W |
TODO
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
The FPGA has two types of GT quads:
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
From FPGA to PC:
Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and purple/blue):
This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview above for more details on the system clock structure.
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s"
Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | |
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C | ||||||||
Clock | |← | ← X → | →| | | X → | →| | | X → | →| | |||||||||||||||
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | ||
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
There is one GTY quad and one GTH quad left over.