Table of contents
Components
FPGA
The FPGA that will be used is XCKU15P-2FFVA1760E from AMD/Xilinx.
- Package mechanical drawing
- FPGA measured 3D model
- Difference between the drawing and 3D model used:
- Total height (A = A1 + A2):
- 3D model is 3.86 mm
- Drawing is 3.71 mm (max)
- Solder ball height (A1):
- 3D model is 0.6 mm
- Drawing is 0.6 mm (max)
- Package height (A2):
- 3D model is 3.26 mm
- Drawing is 3.21 mm (max)
- → It seems that the 3D model of the package we have is not 100% accurate, but the difference (3.86-3.71=0.15 mm) is negligible
- Any thermal interface between the package and the cooling block should be able to "absorb" this difference
- Total height (A = A1 + A2):
Optical transceiver
DC/DC converters
12V vs 24V input?
Clocks
TODO: Simplify the copy of the GT readout platform below
Timing
ADC/DAC
How many ADC channels are needed?
Temperature
Humidity
LDO monitoring
ASIC monitoring
LDOs
Various peripherals
ID
Flash
JTAG
Block diagram
I/O needs
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
GT transceiver signals
The FPGA has two types of GT quads:
- GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
- 8 quads with 4 TX/RX in each for a total of 32 transceivers
- GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
- 11 quads with 4 TX/RX in each for a total of 44 transceivers
LEAP transceivers
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
ASICs
There are 8 high-speed data outputs from each ASIC that can operate of to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
- 6*8=48 RX channels
- 6*1=6 TX channels
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
GT reference clocks
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and blue):
- One for the LEAP channels for the GTY quads 0 to 2
- One for the ASIC RX channels for the GTY quads 4 and 5
- One for the ASIC TX channels for the GTY quads 6 and 7
- One for the ASIC TX channels for the GTH quads 0 to 4
- One for the ASIC TX channels for the GTH quads 5 to 9
This means one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview above for more details on the system clock structure.
Summary
| Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | |
| GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C | ||||||||
| Clock | |← | ← X → | →| | | X → | →| | | X → | →| | |||||||||||||||
| GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | ||
| Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| | ||||||||||||
There are one GTY quad and one GTH quad left over.
Overview
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