DaqMux IP specifications

This is a short specification to help the firmware developer to integrate the DaqMux in his firmware.

Overview

The DaqMux was originally developed as an oscilloscope to transmit streams from the FPGA to software for debugging purposes. Then it started being used as a data streamer by the application to software, and it's configurations were exported to EPICS/software.

Feature summary

The DaqMux can perform the following functionalities

Multiplex up to 4 streams (lanes) and send forward (to software)
Stream packets can be acquired continuously every time a trigger arrives in continuous mode, or only once upon trigger with or without header (meta data) in trigger mode, or many times with or without header (meta data) in trigger mode when auto re-arm is enabled
Possibility of cascading trigger of DaqMux blocks in case streams from several DaqMuxes acquired at the same instant is required
Pause streaming by not overwriting buffers (freeze functionality), therefore nothing is forwarded to software
Down sampling and averaging

Definitions

Stream : a group of bytes transmitted in sequence.
Lane : a physical bus at which the stream crosses
Packet : User abstraction. Bunches of bytes that the user wants forward to software from each lane every time there is a trigger
AXI transaction : Hardware abstraction. Packets are broken into a 1 or more AXI transactions

Applications

Figure 1 shows the DaqMux instantiated in the Common platform firmware in the application side.

Figure 1: Common platform firmware top-level

Generics & IO description

Table 1: DaqMux generics list and description

Generic name	default value	Description
TPD_G	1	Simulation variable; register clock to output delay in nanoseconds
DECIMATOR_EN_G	True	Decimator enable
WAVEFORM_TDATA_BYTES_G	4	Output lane width in bytes
FRAME_BWIDTH_G	10	Power of two, which defines AXI stream transaction size in words (4 bytes)(i.e. when FRAME_BWIDTH_G = 12 → 2¹⁰ x 4 = 4096 bytes)
BAY_INDEX_G	-	Index of the DaqMux
N_DATA_IN_G	16	Number of input data lanes
N_DATA_OUT_G	4	Number of output data lanes

Table 2: IO port list and description

Name	Direction	Clock domain	Width	Description
Clock logic
axiClk	Input	-	1	AXI Lite clock
axiRst	Input	axiClk	1	AXI Lite reset
devClk_i	Input	-	1	Development clock
devRst_i	Input	Synced to devClk_i in DaqMux (for some reason)	1	Development logic reset
wfClk_i	Input	-		Ouput lanes' clock
wfRst_i	Input	wfClk_i		Output lanes' reset
DaqMux control signals and timing information
trigHw_i	Input	Synced to devClk_i in DaqMux	1	Trigger signal to start the DaqMux streaming 0 indicates no trigger event 1 indicates a trigger event
trigCasc_i	Input	Synced to devClk_i in DaqMux	1	Cascaded trigger input. Can be used along with trigHw_i when enabled in the register file 0 indicates no trigger event 1 indicates a trigger event
trigCasc_o	Output	devClk_i	1	Output trigger signal connected to the SW Trigger Enable control register 0 indicates no trigger event 1 indicates a trigger event
armCasc_i	Input	Synced to devClk_i in DaqMux	1	Cascaded trigger Arm. Arms the trigger and prepares DaqMux for trigger arrival 0 indicates no arm 1 indicates armed
armCasc_o	Output	-	1	Output cascade signal connected to the Arm HW Trigger control register 0 indicates no arm 1 indicates armed
freezeHw_i	Input	Synced to devClk_i in DaqMux	1	Adds invalid flag to the streams that are forwarded, and they will be discarded in one of the posterior blocks in the pipeline 0 indicates valid (not freeze) 1 indicates invalid (freeze)
timeStamp_i	Input	Synced to devClk_i in DaqMux	64	Time stamp coming from the AMC carrier core
bsa_i	Input	Synced to devClk_i in DaqMux	128	BSA information coming from the AMC carrier core
dmod_i	Input	Synced to devClk_i in DaqMux	192	Dmod timing information coming from the AMC carrier core
AXI Lite register memory mapped interface
axilReadMaster	Input	axiClk	1	AXI Lite record containing Read Address channel araddr : slv(31 downto 0); arprot : slv(2 downto 0); arvalid : sl; Read data channel rready : sl;
axilReadSlave	Output	axiClk	1	AXI Lite record containing Read Address channel arready : sl; Read data channel rdata : slv(31 downto 0); rresp : slv(1 downto 0); rvalid : sl;
axilWriteMaster	Input	axiClk	1	AXI Lite record containing Write address channel awaddr : slv(31 downto 0); awprot : slv(2 downto 0); awvalid : sl; Write data channel wdata : slv(31 downto 0); wstrb : slv(3 downto 0); wvalid : sl; Write ack channel bready : sl;
axilWriteSlave	Output	axiClk	1	AXI Lite record containing Write address channel awready : sl; Write data channel wready : sl; Write ack channel bresp : slv(1 downto 0); bvalid : sl;
Input lane array
sampleDataArr_i	Input
sampleValidVec_i	Input
linkReadyVec_i	Input

Output lane array
rxAxisMasterArr_o	Output	wfClk_i
rxAxisSlaveArr_i	Input	wfClk_i
rxAxisCtrlArr_i	Input	wfClk_i

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Overview

Feature summary

Definitions

Applications

Generics & IO description

Functional description & block diagrams

Register address mappings and description

Clocking/performance requirements

Connectivity