Group C SVT Setup

Useful Links

SVT EPICS Power Instructions

DAQ & Power Mapping in Group C

Operation

!!! Remember to make sure the detector is being cooled. !!!

!!! Remember to make sure the interlocks are in the state you want them. !!!

Logbook

1/14/2013

System status (from Ben's email Jan 7th):
We can currently power 8 FEBS. We can power every hybrid attached to those 8 FEBS: 30 Hybrids. All Hybrids that we can power are able to sync, except for FEB 8, Hybrid 2, which has just 1 APV that won’t sync.
Link to excel file. 

L1t (DAQ FEB #0 and GUI FEB #0) has what looks like a short on the output side of the regulator on DVDD (we can’t see the short probing the pins from outside).
L6b (DAQ FEB #5 and GUI FEB #7) first appeared to have a short on DVDD. After 5mins and a power cycle it came back with current levels that looked reasonable except that the DVDD level indicated it had no control link. 

10:00AM
Danh Du finished terminating the pigtails from the flange boards. We are missing a single female pin on one REDEL connector. Its wire was cut and folded back waiting for new pins. He did not test the pinout at this point.

11:00AM
Removing FEB cooling plate from SVT box to rework FEBs.

12:54PM
Extracted thee FEB cold plate and removed all FEBs. The two non-working FEBs (L1t and L6b) were sent to Ben directly; the other were given to Lupe for rework.
The default rework is to add Zener diodes to all FEBs and also to remove the FPGA LED that is always on (it's on the cooling plate side so we can't see it anyway; it indicates FPGA programming OK).
I added the serial number of each board to the mapping on the DAQ & Power Mapping in Group C page.

4.00pm
Found that P5 connector had DIG_GND swapped across the flange. The two pigtail connector seemed ok (the twisted pair went into adjacent pins as expected) which leaves the only possibility of having a swap at the pads on either side of the flange board.
=>Danh Du corrected this on the air side P5 connector.

5.15pm
Placed FEB L1t on cold plate next to the SVT box and connected P1 power cable. Without detector attached the FEB powers up fine with expected currents. When connecting the L1t detectors we see again a 3A current on DIG as before. We also tried connecting L1-3 spare half-modules with the same result. We then swapped out P1 with P5 and powered the FEB as if it was L1b. This was successful. Thus the problem points to some problem in the L1t power cable. Tomorrow we need to ohm out that path to see if we can find a problem.

6:30 p.m.
L1t, L6t and L6b modules have been tested with the single-FEB setup. All OK.

Equipment

Interlock board

see Group C interlock board for instructions on monitoring and controls.

Serial portserver

Digi Portserver TS 4: 192.168.1.217 on LAN. Telnet from ppa-pc91245, e.g. "telnet 192.168.1.217 2001" will connect you to port 2001. All serial ports are logged to /var/log/portserver on ppa-pc91245. Configure the portserver using its web interface or Telnet. Docs: http://www.digi.com/support/productdetail?pid=1954

Thermoelectric chiller (backup chiller for FEB)

Oasis 190: manual

Error bits:

Procedures

Basic instructions to take a pedestal run with CODA

To be added.

Miscellaneous

Reloading PGP card drivers

Typically after a reboot we need to reload the pgp card driver. 

$ cd /u1/pgpcard/software/driver_old/

$ ./pgpcard_load

OLD:Take a calibration run with expert SVT GUI

Start the DAQ:

$ cd /u1/software/software_new

$ source setup_env.csh

$ ./bin/frontEndTestGui

Click <read status> and make sure no error is seen. If so, check that the FEB is powered correctly.

Make sure the AxiXadc temperature is ok (50-60C).

Configure with config/FrontEndBoardConfigC01.xml

Click <read status> and check that more registers are found.

Turn on power to hybrids (see below)

Do a hard reset under commands/FebCore/HybridHardReset (current on AVDDP should drop ~100mA).

Click <Write config>.

Do a soft reset under commands/FebCore/HybridSoftReset.

Check that the hybrid currents measured are ok. Sync status for each channel can be seen in register RceCore/DataPath[x]/Synced, 1xf for powered channels.

Test Run SVT Group C Setup

Group C SVT test setup