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You can also open terminal windows in the FastX browser so that they stay alive when you close FastX. You will need to tunnel into itkpix@felix via <user>@rddev111.slac.stanford.edu.
GBCR Documentations
- GBCR PDR SPR and PDR (2019): Indico (Sep/12/2019), Documentation collection and report (Nov/3/2019)
- GBCR2 Specification document (register details) Nov/2019
- GBCR Testing Github
- GBCR status Jan/2023 (Jingo Ye)
The initial distribution of Optoboards to Inner System in Aug/2022 are Optoboard V2.1 with GBCR2. CMD downlink drive pre-emphasis has design issues that increased jitter to trade for some pre-emphasis. GBCR V3 design updates triplicated EQ design blocks to improve SEE immunity, and also removed passive attenuator. V3 also had another attempt to address the CMD TX design issues but dropping the DCoffset-cancellation logic due to the lack of space made the logic problematic still. The system baseline is to deploy GBCR V3 in Optoboard V4 where the GBCR CMD TX is bypassed. However, this bypass is only available in optoboard version V3 and higher.
A summary of the key GBCR control registers (based on GBCR spec document V1.2.3 from Nov/2022). There are 3 registers per GBCR input channel for independent EQ controls of each channel and another 11 registers for coming controls of retime mode and TX pre-emphasis:
| Address | Default | Bits | Name | Function |
|---|---|---|---|---|
| 0 | 0x1F | 0-2 | ch1CML_AmlSel<2:0> | Output amplitude of input RX channel 1 |
| 3-4 | ch1EQ_ATT<1:0> | EQ attenuator for input RX channel 1. | ||
| 5 | ch1dis_EQ_LF | Diable Low Frequency CTLE stage for RX inpyt channels 1. | ||
| 6-7 | NC | |||
| 1 | 0xBB | 0-3 | ch1CTLE_MFSR<3:0> | Middle frequency (0.2-0.4 GHz) peaking strength |
| 4-7 | ch1CTLE_HFSR<3:0> | High frequency (0.4-1.6 GHz) peaking strength | ||
| 2 | 0x02 | 0 | ch1disLPF | Disable DC offset cancellation in RX input channels 1 |
| 1 | ch1disDFF | Disable DFF in input RX channel 1. RX channel works in equalizer mode. | ||
| 2 | ch1Dis | Disable RX input channel 1 | ||
| 3-7 | NC | |||
| 3-5 | Same block of registers for RX input channel 2 as address 0-2 for channel 1 | |||
| 6-8 | Same block of registers for RX input channel 3 as address 0-2 for channel 1 | |||
| 9-11 | Same block of registers for RX input channel 4 as address 0-2 for channel 1 | |||
| 12-14 | Same block of registers for RX input channel 5 as address 0-2 for channel 1 | |||
| 15-17 | Same block of registers for RX input channel 6 as address 0-2 for channel 1 | |||
| 18-20 | NC | Same block of registers for RX input channel 7 as address 0-2 for channel 1 | ||
| 21 | 0x02 | 0 | dllCapRest | Reset control voltage in DLL. |
| 1 | dllEnable | Enable DLL in phase shifter | ||
| 22 | 0x0F | 0-3 | dllChargePumpCurrent<3:0> | Set charge pump current |
| 4 | dllForceDown | Force down charge pump output | ||
| 5-7 | NC | |||
| 23 | 0x33 | 0-3 | dllClockDelayCh6<3:0> | Config clock delay of channel 6 |
| 4-7 | dllClockDelayCh7<3:0> | Config clock delay of channel 7 | ||
| 24 | 0x33 | Similar dllClockDelay control for channel 4,5 | ||
| 25 | 0x33 | Similar dllClockDelay control for channel 2,3 | ||
| 26 | 0x33 | Similar dllClockDelay control for channel 0,1 | ||
| 27 | 0x70 | 0 | disTestCK | Disable Test clock output |
| 1-2 | CLK_Rx_EQ<1:0> | Config passive EQ in eRx for input clock | ||
| 3 | CLK_Rx_invData | Invert output data of eRx for input clock | ||
| 4 | CLK_Rx_enTermination | Enable the termination resistors of eRx for input clock | ||
| 5 | CLK_Rx_setCM | Set common mode voltage of eRx for input clock | ||
| 6 | CLK_Rx_En | Enable eRx doe input clock | ||
| 7 | NC |
Some Useful Links
- Optoboard System Documentation
- FELIX JIRA (Oct/22) on optoboard + ITkPix readout setup
- CERN mattermost Bern-Optoboard channel
- Talk (Dec/9/2022) by Angira Rastogi on Optoboard-FELIX setup at LBNL
GBCR Documentations
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