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By swapping fibers I determined the problem was on the FIM side (not DAQ/DRP node) or in the fiber transport to the DAQ (receiving power measured -10dBm at the DRP). In the end power cycling fim1 seemed to solve the problem. Much later (Jan 31, 2023) I have a feeling the solution for this problem might have been fixing a ground loop by using an AC-coupled power supply instead of a DC-coupled supply, but I could be wrong -cpo.
Dropped Configure Phase2
- Fixed once by toggling between XpmMini timing and LCLS2 timing (similar to Opals). Timing link looked good before this and TxLinkReset didn't help.
- Also saw this when the Partition register was set via epics before the timing system was initialized, causing later epics-writes to the Partition register to silently fail, I believe (see https://github.com/slac-lcls/lcls2/blob/9828bbd3238ff9d534ec77b421aefe956276dcc5/psdaq/psdaq/configdb/wave8_config.py#L415)
Crashes
If you see this crash at startup it is an indication that the fim IOC that writes these registers is not up and running:
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