Page History

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FEB	FEB SN	Flange Board (HW)	Flange Channel	I At Boot (AnaN, AnaP, Digi)	I Mod ON	I Mod ON + Config	Ctrl Ch (dpm / ch) (1 is top cob)	Fiber (ctrl / Data)	jTag OK	Feb Address	Data Taking	Comment
L0-1t	12	2	2	0.242 - 1.212 - 1.250	0.292 - 2.317 - 1.392	0.292 - 2.833 - 1.322	0 / 3	D / H	Y	0	OK
L2-3t	17	3	0	0.256 - 1.248 - 1.239	0.317 - 2.319 - 1.314	0.313 - 3.112 - 1.313	0 / 8	D / H	Y	2	OK
L5t	05	0	0	0.236 - 1.216 - 1.287	0.272 - 2.101 - 1.334	0.271 - 2.715 - 1.334	1 / 5	A / E	Y	6	OK
L6t	16	0	1	0.249 - 1.222 - 1.362	0.313 - 2.743 - 1.434	0.308 - 3.539 - 1.434	1 / 4	A / E	Y	8	OK
L4b ( In EPICS is L4t)	11?08	2	1	0.248 - 1.241 - 1.248			0 / 4	C / G	Y	5	OK	Hybrid 1 and Hybrid 3 give check transaction errors at the power up and configuration. Feb issue? Also noticed two HV pins missing.
L4t ( In EPICS is L4b)	08?11	1	0	0.252 1.153 1.374	0.307 - 2.8755 - 1.448	0.304 - 3.564 - 1.449	1 / 8	B / F	Y	4	OK
L5b	20	1	1	0.246 - 1.169 - 1.243	0.306 - 2.242 - 1.346	0.302 - 3.063 - 1.321	1 / 7	B / F	Y	7	OK
L6b	04	1	2	0.248-1.199-1.278	0.307 - 2.705 -1.345	0.304 - 3.525 - 1.348	1 / 6	B / F	Y	9	OK
L0-1b	07	2	0	0.241 - 1.284 - 1.313	0.293 - 2.235 - 1.394	0.293 - 2.931 - 1.394	0 / 5	C / G	Y	1	OK
L2-3b	14	3	1	0.248 - 1.122 - 1.195	0.308 - 2.324 - 1.267	0.305 - 3.153 - 1.267	0 / 7	D / H	Y	3	OK	Timeouts on DPM at first test. After reseating the miniSAS cable (both feb and flange board) data taking was clean. AVDD pin return sense bent

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