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Word# | BITS | Name | Description | Note |
---|---|---|---|---|
0 | [7:0] | Version[7:0] | Module's SRP Version number | Always respond with local value |
0 | [9:8] | OpCode[1:0] | Operation Code | Echoed back |
0 | [10] | UnalignedAccess | Module's support for non word-aligned addresses |
|
0 | [11] | MinAccessSize | Module's byte/word transaction support |
|
0 | [12] | WriteEn | Module Write op support |
|
0 | [13] | ReadEn | Module Read op support |
|
0 | [14:14] | IgnoreMemResp | Ignore Memory Response | Echoed back |
0 | [20:15] | Reserved | Reserved | Responds back with 0x0 |
0 | [23:21] | Prot[2:0] | Protection control | Echoed back |
0 | [31:24] | TimeoutCnt[7:0] | Timeout Counter | Echoed back |
1 | [31:0] | TID[31:0] | Transaction ID | Echoed back |
2 | [31:0] | Addr[31:0] | Register Address | Echoed back |
3 | [31:0] | Addr[63:32] | Register Address | Echoed back |
4 | [31:0] | ReqSize[31:0] | Request Size | Echoed back |
5 | [31:0] | MemData[31:0] | Memory Data | Only used for non-posted operations |
... | ... | ... | ... | Only used for non-posted operations |
4+CEIL((ReqSize+1)/4) | [31:0] | MemData[31:0] | Memory Data | Only used for non-posted operations |
5+CEIL((ReqSize+1)/4) | [7:0] | MemResp[7:0] | Memory Bus Response | Footer :
Each SRP bus bridge implementation will define it's own use for this field. |
5+CEIL((ReqSize+1)/4) | [8] | timeout | timeout error | Footer |
5+CEIL((ReqSize+1)/4) | [9] | eofe | End of Frame with Error | Footer |
5+CEIL((ReqSize+1)/4) | [10] | frameError | Framing error detected | Footer |
5+CEIL((ReqSize+1)/4) | [11] | verMismatch | Version Mismatch Error | Footer |
5+CEIL((ReqSize+1)/4) | [12] | ReqError | Request Error | Footer. Tried to perform unsupported request such as:
|
5+CEIL((ReqSize+1)/4) | [13] | HwBusLock | Hardware Bus Lock | |
5+CEIL((ReqSize+1)/4) | [31:1314] | Reserved | Always zeros | Footer |
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