SRP Version 3

Requirements

  • Support an AXI4-Lite and AXI4 firmware modules
    • SrpV3AxiLite.vhd will only support 32-bit transactions and 32-bit alignment
    • For applications that need non 32-bit transactions or non 32-bit alignment for AXI-Lite, we can achieve this by bridging the SrpV3Axi.vhd with the AxiToAxiLite.vhd
  • Echos back the AXI stream's TDEST
  • Header will include:
    • SRP Version number: (8-bits)
      • Always echo backs the local version (0x03)
    • OP-Code: Non-Posted Read, Non-Posted Write, Posted Write, NULL (2-bit)
    • Non 32-bit address alignment support (1-bit)
    • Non 32-bit transaction alignment support (1-bit)
    • Reserved (12-bit)
    • Timeout counter (8-bit)
      • In units of 100 ms
      • If 0x0, no time out
    • Transaction ID: (32-bits)
    • Base Address of bursting (64-bits)
    • Request Size  (32-bit)
      • In units of bytes
      • Max. read size is 232
      • Max. write size is 212
  • Header will be echoed except for:
    • SRP Verson number
  • Footer will be 32-bit, zero on success, and will include:
    • Memory Bus response (8-bit)
      • success == 0x0
      • failed != 0x0
    • Timeout flag (1-bit)
    • Request's EOFE (1-bit)
    • Version Mismatch (1-bit)
    • Invalid request size (1-bit)
    • All other bits must be 0x0
  • 32-bit data register transactions
    • Byte aligned access
    • Read and Write transactions supported
    • Set and Clear transactions NOT supported
    • Read Modify Write NOT supported
  • 64-bit address space
    • 64-bit required for >4 GB DDR memory
  • Support single and bursting transactions
    • Support up to 232 byte read burst transactions
    • Support up to 212 byte write burst transactions
    • Only support contiguous bursting
  • If inbound request (non-posted) is received and EOFE, the SRP firmware will not perform read/write transaction and respond back.
    • Requires caching up the transaction (Set AxiStreamFifo's VALID_THOLD_G = 0)
    • While caching: If the FIFO is full and no request frame detected (SOF + EOF), then the SRP firmware will drain the FIFO
  • If inbound request is received with version number not equal to the protocol, the SRP firmware will not perform read/write transaction and respond back
  • Notes on software processing of the response frame:
    • Check for a non-zero footer
    • Check the received frame size matches the the expected size
      • Firmware is allowed to drop the MemData in response frame and immediately send footer if error bus responds received
    • Check the echo'd back [header, address, TID, ReqSize] matches request frame

Incoming Request

Word#BITSNameDescriptionNote
0[7:0]Version[7:0]SRP Version number
0[9:8]OpCode[1:0]Operation Code
  • 0x0=Non-Posted Read
  • 0x1=Non-Posted Write
  • 0x2=Posted Write
  • 0x3=NULL
0[13:10]Reserved for RespondsReserved for RespondsIgnored
0[14:14]IgnoreMemRespIgnore Memory Response
0[20:11]Reserved (Spare)Reserved (Spare)Ignored
0[23:21]Prot[2:0]Protection control
  • For AXI write: awprot[2:0]
  • For AXI read: arprot[2:0]
0[31:24]TimeoutCnt[7:0]Timeout Counter
  • If 0x00, then no timeout
  • In units of 100 ms
1[31:0]TID[31:0]Transaction ID
2[31:0]Addr[31:0]Register AddressIn units of bytes
3[31:0]Addr[63:32]Register AddressIn units of bytes
4[31:0]ReqSize[31:0]Request Size
  • In units of bytes
  • Counting from zero
  • ReqSize = 0x0 is 1 byte request
5[31:0]WriteData[31:0]Write DataOnly used for write operations
............Only used for write operations
4+CEIL((ReqSize+1)/4)[31:0]WriteData[31:0]Write DataOnly used for write operations

Outgoing Response

Word#BITSNameDescriptionNote
0[7:0]Version[7:0]Module's SRP Version numberAlways respond with local value
0[9:8]OpCode[1:0]Operation CodeEchoed back
0[10]UnalignedAccessModule's support for non word-aligned addresses
  • Always respond with local value
  • 0 = not supported (only 32-bit alignment)
  • 1 = supported (byte alignment)
0[11]MinAccessSizeModule's byte/word transaction support
  • Always respond with local value
  • 0 = 32-bit (4 byte) transactions only
  • 1 = Byte level transactions allowed
0[12]WriteEnModule Write op support
  • Always respond with local value
  • 0 = write operations are not supported
  • 1 = write operations are supported
  • Applies to both posted and non-posted writes
0[13]ReadEnModule Read op support
  • Always respond with local value
  • 0 = read operations are not supported
  • 1 = read operations are supported
0[14:14]IgnoreMemRespIgnore Memory ResponseEchoed back
0[20:15]ReservedReservedResponds back with 0x0
0[23:21]Prot[2:0]Protection controlEchoed back
0[31:24]TimeoutCnt[7:0]Timeout CounterEchoed back
1[31:0]TID[31:0]Transaction IDEchoed back
2[31:0]Addr[31:0]Register AddressEchoed back
3[31:0]Addr[63:32]Register AddressEchoed back
4[31:0]ReqSize[31:0]Request SizeEchoed back
5[31:0]MemData[31:0]Memory DataOnly used for non-posted operations
............Only used for non-posted operations
4+CEIL((ReqSize+1)/4)[31:0]MemData[31:0]Memory DataOnly used for non-posted operations
5+CEIL((ReqSize+1)/4)[7:0]MemResp[7:0]Memory Bus ResponseFooter :
  • if MemResp == 0, then success
  • if MemResp != 0, then failed

Each SRP bus bridge implementation will define it's own use for this field.

5+CEIL((ReqSize+1)/4)[8]timeouttimeout errorFooter
5+CEIL((ReqSize+1)/4)[9]eofeEnd of Frame with ErrorFooter
5+CEIL((ReqSize+1)/4)[10]frameErrorFraming error detectedFooter
5+CEIL((ReqSize+1)/4)[11]verMismatchVersion Mismatch ErrorFooter
5+CEIL((ReqSize+1)/4)[12]ReqErrorRequest Error

Footer.

Tried to perform unsupported request such as:

  • Incorrect access size
  • Unaligned access
  • Write access with writes disabled
  • Read access with reads disabled
5+CEIL((ReqSize+1)/4)[13]HwBusLockHardware Bus Lock
5+CEIL((ReqSize+1)/4)[31:14]ReservedAlways zerosFooter

Contact

Ben Reese

bareese@slac.stanford.edu

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