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When mounting the boards on Friday 1/15 the top and bottom FEBs were swapped for L1 and L2-3. Since there is no particular reason yet for having a specific FEB processing a particular layer we will keep this as the new layout.  Therefore all testing on Saturday was with this new layout. This has been updated on the DAQ & Power Mapping in Group C page.

11:00AM-17:00AM

Status update for today:
 We are able to get sync on all of the FEBs with the stack of spare hybrids. We might have had an issue with not setting the power configuration correctly yesterday which means that the hybrids might have gotten up in some funny state. It’s unclear, but doing it the right way seem to solve all the issues. 

All flange channel were working. The issue with the two channels we didn’t see any control link on was a firmware issue. On the control dpm we only accepted 10 links and the channels that we were using happened to be on two unused channels. Ben changed the firmware to accept 12 inputs and things got solved. We put the flange back together again after that as it was. 

 Clarification: At the moment, we don't know if the two channels on flange board 0 are working or not.  The only thing we were able to do before leaving for the day was to switch the high speed cable from the flange channels that were not working to those that weren't being used.  This allowed us to verify that the two unused channels on flanges 2 and 3 were working as expected.  Ben changed the firmware such that all flange channels are accepted by the control DPM but it was never loaded and tested.  We were hoping to do this first thing tomorrow morning if possible, but it can also be done once the FEB support plate is loaded in the SVTbox.
I tested 5 spare flange boards today and 4 of them (flange boards 4,5,6, and 8) are fine.  I only let the system run for a few minutes with each board connected, but, during that time, no errors were observed on the control link and very little to no errors were observed on the data links.  One of the boards (flange board 7) was a bit flaky.  When I initially tested it, there was a large amount of errors on DPM 0, data path 1 and DPM 3, data path 1.  I then powered cycled everything and re-seated the high speed cables and the errors on the two previous DPM's went away, but several errors began appearing onDPM 2, data path 1.  I decided to power cycle and re-seat the cables again and, this time, the errors went away.  I also switched the high speed cables connected to flange channels 1 and 2 and there were no errors.  Maybe Ben or Ryan can give their thoughts as to what might have caused the large amount of errors that were present initially.  

 We are ready to put the FEB cooling plate into the detector and hook up the detectors to continue testing. 

Equipment

Interlock board

see Group C interlock board for instructions on monitoring and controls.

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