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Ryan showed an initial schematic of a flange board. It was digital flange board i.e. no LV or HV power, handling 3 FE boards. The initial idea of physical layout was blocked out here: http://www.slac.stanford.edu/~rherbst/projects/heavyp/doc/flange_test.jpg^{Image Removed}
He would make an attempt of estimating the height of each board.
We would need 4 of these and thus have 2 spare FE board channel sets.
Ryan also discussed the options for how to group the optical channels on the RTM. The preferred option is to have a patch panel to allow more flexibility in the layout. This would help in reorganizing channels if there are problems. The other option would be to build a custom RTM to handle our input.
He mentioned that LSST will use a similar flange solution and that we should investigate how to leverage the R&D with them.

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