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Items in square brackets (\[\]) are optional.

Initial instruction

• Execution after reset starts at 0xfffffffc
  • A branch instruction (either b or ba; 26 bit range) to some boot code is loaded here
    • The Xilinx example branches to in block RAM (bram) at 0xffffff00
    • The RTEMS example branches to download_entry (but I'm not sure how)
  • Potentially a sc (system call) instruction could be loaded here? Any advantage to this?
    • Probably not as the corresponding ivor register (PPC 440) is not loaded yet
    • The PPC 405 doesn't have ivor registers, so it would continue executing at the system call vector

dlEntry.s

This file is considered part of an RTEMS BSP and can be found in $RTEMS_ROOT/src/c/src/lib/libbsp/powerpc/virtex5/dlentry. What's written here is written for the PPC 440 found in Xilinx Virtex 5 parts. The Virtex 4 version is similar.

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• Announce what's running
• Configure the network from DHCP
• Set up the dynamic linker

• Wiki Markup
  \[Start the shell\]

• Wiki Markup
  \[Start the debugger daemon ({{gdb}} stub)\]

• Create a Task
• Determine what the Task should run
  • Read metadata from flash
  • Read the front panel rotary switch
• Dynamically link the code
• Run the Task