Page History

...

• Execution after reset starts at 0xfffffffc
  • A branch instruction (either b or ba; 26 bit range) to some boot code is loaded here
    • The Xilinx example branches to in block RAM (bram) at 0xffffff00
    • The RTEMS example branches to download_entry (but I'm not sure how)
  • Potentially a sc (system call) instruction could be loaded here? Any advantage to this?
    • Probably not as the corresponding ivor register (PPC 440) is not loaded yet
    • The PPC 405 doesn't have ivor registers, so it would continue executing at the system call vector

dlEntry.s

...

This is considered part of an RTEMS BSP. What's written here This portion is written for the PPC 440 found in Xilinx Virtex 5 parts. The Virtex 4 version is similar.

...