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Items in square brackets (\[\]) are optional.

Initial instruction

• Execution after reset starts at 0xfffffffc
  • A branch instruction (either b or ba; 26 bit ramge) to some boot code is loaded here
    • The Xilinx example branches to in block RAM (bram) at 0xffffff00
    • The RTEMS example branches to download_entry (but I'm not sure how)
  • Potentially a sc (system call) instruction could be loaded here? Any advantage to this?
    • Probably not as the corresponding ivor register (PPC 440) is not loaded yet
    • The PPC 405 doesn't have ivor registers, so it would continue executing at the system call vector

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• Set up an RTEMS extension that creates and manages the syslog

RcePic

• Set up a single PIC Manager
  • Set up PEBs
  • Set up ECDs
  • Set up FLBs
  • Set up PIBs
  • Install a BOOKE Critical exception handler
  • Install an External Interrupt handler

RceEthernet

RceBsdnet

Init task

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