| Note |
|---|
In Note that in this description, time advances down along the page. Bear in mind as well that this description applies to the gen 1 instances of the system. |
Initial instruction
- Execution after reset starts at 0xfffffffc
- A branch instruction (either
borba; 26 bit ramge) to some boot code is loaded here- The Xilinx example branches to in block RAM (
bram) at 0xffffff00 - The RTEMS example branches to
download_entry(but I'm not sure how)
- The Xilinx example branches to in block RAM (
- Potentially a
sc(system call) instruction could be loaded here? Any advantage to this?- Probably not as the corresponding
ivorregister (PPC 440) is not loaded yet - The PPC 405 doesn't have
ivorregisters, so it would continue executing at the system call vector
- Probably not as the corresponding
- A branch instruction (either
...