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The frame received by software will contain a series of trigger frames as output from the Firmware Event Builder. The number of event builder frames will be determined by the configured block size (N).
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First a single Trigger Block Header will be included
- Batcher Header receive per Trigger Block Header (64-bits) - Batcher superframe header
- Trigger Block Header Word 0 (32-bits)
- 31:16 = 0x0000
- 15:08 = Sequence # (running, spans each run)
- 07:04 = 0x2 (64-bits)
- 03:00 = 0x1 (version 1)
- Trigger Block Header Word 1 (32-bits)
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- Event Builder Header 0 (32-bits)
- Event Builder Header 1 (32-bits)
- 31:08 = 0x000000
- 07:00 = RCE Address
- Event Builder Header 2/3 (64-bits)
- 63:00 = Timestamp
- A 64-bit running counter gets reset to 0 at the start of each run
- This number will be the same across all DPMs for a given trigger event
- MultiSample Data ( N M * 4 * 32-bits) (M depends on data reduction)
- Event Builder Tail - (32-bits)
- 27: FIFO backup error (Should only see skip counts if this is 1)
- 26: ApvBufferAddressSyncError - APV frames didn't have the same addresses
- 23:12: SkipCount - Number of MultiSamples that got dumped due to FIFO backup
- 11:00: Number of MultiSamples (M)
- Per Trigger Tail Word 0 (32-bits) - Batcher sub-frame tail 0
- 31:00: Number of valid bytes in data section, excluding tail (2 * 4 + N M * 16)
- Per Trigger Tail Word 1 (32-bits) - Batcher sub-frame tail 1
- 31:24: 0x7 (Number of valid bytes last 64-bit word) (can be ignored)
- 23:17: 0x00 (Unused TUSER_LAST)
- 16: Error Flag
- 15:08: 0x00 (Unused TUSER_FIRST)
- 07:00: 0x00 (Unused TDEST Field)
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