Versions Compared

Old Version 666

changes.mady.by.user Sandberg, Hampus

Saved on

compared with

New Version Current

changes.mady.by.user Sandberg, Hampus

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.
Tip

The GT Readout Platform aims to provide a readout for use with new pixel detectors developed at SLAC (≥ 2023), which use high-speed (> 1 Gbit/s) gigabit transceivers for their data output. See for example the SparkPix-IO prototype.

It consists of three main parts (shown in the block diagram below):

  • Digital board with FPGA and a multi-channel high-speed optical transceivers for external communication
  • Analog board with control and monitoring circuitry of the ASICs as well as power supplies
  • Carrier board with up to four ASICs

The sections below describe the platform in more detail. Use the table of contents below to quickly find a specific section you might be looking for or use one of the useful resources on the right for quick access.

Gliffy Diagram
macroIdd09e01e1-74c8-41ff-be1d-9e77d2782771
displayNamegt-readout-platform-overview
namegt-readout-platform-overview
pagePin5

Table of contents

Table of Contents
maxLevel2
exclude\b(?:Table of contents|Useful resources|Pages under this one)\b|\*

Useful resources

Pages under this one

Children Display

ASIC level requirements summary

RequirementePixUHRSparkPix-SSparkPix-ED (question)
Frame rate100 kfps1 Mfps1 Mfps
Power supplies

2.5 V Analog
1.3 V (AS/DS/IO)

2.5 V Analog
1.3 V (AS/DS/IO)
 0.6 V (Current sink!)

1.3 V (AS/DS/IO)
Power for each supplyePixUHR - 35 kHzSparkPix-S: supply/ground and power consumptiont.b.d.
Number of GT IOs per ASIC

8 (outputs)
1 clock in

8 (outputs)
1 clock in

t.b.d
(The current agreement is to have 8 outputs)

Expected I/O speed5.25 Gbit/s5.25 Gbit/s10 Gbit/s (question)

Total data bandwidth

42 Gbit/s42 Gbit/s80 Gbit/s(question)

Target Cameras

There are three targeted cameras for this project:

  • 2x2 ePix/SparkPix
  • 1M ePix to later be used as building block for 16M camera
  • 2M SparkPix

Block diagrams

2x2 ePix/SparkPix

  • ePixHR/UHR 2x2 would be 140k pixels
  • SparkPix S would be 500k pixels

Gliffy Diagram
displayName2x2-block-diagram
name2x2-block-diagram
pagePin5

Expand
titleArchived block diagrams

1M ePix

  • ePixHR/UHR in a 6x6 configuration would be 1.1M pixels
  • ePixHR/UHR in a 6x5 configuration would be 1M pixels

Gliffy Diagram
size300
displayName1M-block-diagram
name1M-block-diagram
pagePin6

Expand
titleArchived block diagrams

2M SparkPix S

  • SparkPix S in a 4 x 4 configuration would be 2M pixels

Gliffy Diagram
size300
displayName2M-block-diagram
name2M-block-diagram
pagePin2

Parameter overview


2x2 ePix/SparkPix

1M ePix

2M SparkPix S

Parameter (estimated)

Small Camera 
ePixHR /UHR – 140k
 2x2 ASIC

Small Camera 
SparkPix S – 500k
 2x2 ASIC

Super tile
ePixHR /UHR – 1M
 6x5 ASIC

Super tile
ePixHR /UHR – 1.1M
 6x6 ASIC

Quad Camera 
SparkPix S – 2M
 4x4 ASIC

Pixels

129,024 px
(168 *192*4)

540516,672 096 px
(352336*384*4)

967,680
(168 *192*30)

1,161,216 px
(168 *192*36)

2,162064,688 384 px
(352336*384*16)

Rate

35 kHz / 100 kHz

1 MHz

35 kHz / 100 kHz

35 kHz / 100 kHz

1 MHz

Focal Plane Area

4 cm x 4 cm

4 cm x 4 cm

12 cm x 10 cm

12 cm x 12 cm

8 cm x 8 cm

Front side footprint (window)

5 cm x 5 cm

5 cm x 5 cm

14 cm x 1 2cm

14 cm x 14 cm

10 cm x 10 cm

Power (only ASIC)

0.016 kW/???

0.021 kW0.130 kW/???0.144 kW/???0.084 kW

Weight

1.5 kg

1.5 kg

9 kg

10 kg

6 kg

Data volume 

56 Gbit/s/ 160 Gbit/s

160 Gbit/s

420 Gbit/s / 1190 Gbit/s

504 Gbit/s / 1440 Gbit/s

640 Gbit/s

Expand
titleePixUHR Throughput Calculations

From ASIC to FPGA

          168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame

@35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbit/s

@100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbit/s

From FPGA to PC

168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame

@32k - 1 ASIC (35kHz/100kHz): 14 Gbit/s / 40 Gbit/s

@140k - 4 ASIC (35kHz/100kHz): 56 Gbit/s / 160 Gbit/s

@1M - 30 ASIC (35kHz/100kHz): 420 Gbit/s / 1.19 Tbit/s

@1.1M - 36 ASIC (35kHz/100kHz): 504 Gbit/s / 1.44 Tbit/s

@4M - 144 ASIC (35kHz/100kHz): 2 Tbit/s/ 5.76 Tbit/s

@16M - 576 ASIC (35kHz/100kHz): 8.1 Tbit/s / 23 Tbit/s

ASIC Power Requirements

ASIC Power Requirement

Analog Section

Digital Section

I/O Section

0.6V Sink

Analog TPS

ePixUHR 140k 2x2 Detector

SparkPix-S 500k 2x2 Detector

ePixUHR 140k 2x2 Detector

SparkPix-S 500k 2x2 Detector

ePixUHR 140k 2x2 Detector

SparkPix-S 500k 2x2 Detector

ePixUHR 140k 2x2 Detector

SparkPix-S 500k 2x2 Detector

ePixUHR 140k 2x2 Detector

SparkPix-S 500k 2x2 Detector

Voltage

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

??? MaybeN/A

0.6 V

2.5 V

2.5 V

Required current

10A

(= 2.5 A * 4 ASIC)

13.4 A

(= 3.35A 35 A * 4 ASIC)- Old digital design:

1.2 872 A

(= 0.3 468 A * 4 ASIC)
-New digital design

????

- Old digital design

2.0 A

(= 0.5 A * 4 ASIC)-New digital design

????

TBD

1.6 A

(= 0.4 * 4 ASIC)

[1RX, 8TX, 8serializer and 2cm clkspine : ~ 317mA]


??? (If existing lower or equal than SparkPixS)N/A

-8 A
(= -2A * 4 ASIC) 

0.4 A

(=0.1 * 4 ASIC) 


System Requirement

+1.3 V @ +17.5 A

(Adding +30% current for PVT variation)

+1.3 V @ +3 A

(Adding +30% current for PVT variation)

[waiting for the new digital design] 

+1.3 V @ +2.5 A

(Adding +30% current for PVT variation)

+0.6 V @ -11 A

This current is not provided by the LDO. But it passes through it.

(Adding +30% current for PVT variation)

+2.5 V @ +0.5 A

(Adding +30% current for PVT variation)

FPGA

Selection

Expand the sections below to see additional information about the FPGA that was selected for this project.


Expand
titleFPGA Selection

ePixUHR 140k

ePixUHR 140k

2x2 Detector

Specs

ePixUHR 1.1M

6x6 Detector

Specs

ePixUHR 1M

6x5 Detector

Specs

SparkPix-S 500k

2x2 Detector

Specs

SparkPix-S 2M

4x4 Detector

Specs

KU15P (-A1760)

Kintex Ultrascale+

KU15P (-A1156)

Kintex Ultrascale+

FPGA USED IN ePixHR250M

KU15P (-E1517)

Kintex Ultrascale+

XCVU160 (-C2104)

Virtex Ultrascale

XCVU190 (- A2577 )

Virtex Ultrascale

VU13P (-A2577)

Virtex Ultrascale+

General IO (HD, HP)






96 HD, 416 HP

48 HD, 486 HP

96 HD, 416 HP

52 HD, 364 HP

0 HD, 448 HP

0 HD, 448 HP

High Speed GTs (GTH/GTY)

- ASIC data:

32 = 8 lanes * 4 ASIC

- Spare outputs :

4

- PGP communication:

12 = 12* 160 Gbit/s / 275Gbit/s

(1 Amphenol Transceiver)

Total:

48 High Speed GTs

- ASIC data:

288 = 8 lanes * 36 ASIC

- Spare outputs :

0

- PGP communication:

72 = 12* 1.44 Tbit/s / 275Gbit/s

(6 Amphenol Transceivers)

Total:

360 High Speed GTs

- ASIC data:

240 = 8 lanes * 30 ASIC

- Spare outputs :

0

- PGP communication:

72 = 12 lanes * 1.19 Tbit/s / 275Gbit/s

(6 Amphenol Transceivers)

Suggested 3 transceivers 1.4x compression in the detector

Total:

312 High Speed GTs

(If considering 5x2 Modules, 104 GTs each)


- ASIC data:

32 = 8 lanes * 4 ASIC

- Spare outputs :

4

- PGP communication:

12 = 12* 160 Gbit/s / 275Gbit/s

(1 Amphenol Transceivers)

Total:

48 High Speed GTs

- ASIC data:

128 = 8 lanes * 16 ASIC

- Spare outputs :

0

- PGP communication:

24* = 12* 495 Gbit/s / 275Gbit/s

(2 Amphenol Transceivers)

Total:

152 High Speed GTs

76

(44 GTH/32 GTY)

28
(20 GTH/8 GTY)

56

(32 GTH/24 GTY)

104

(52 GTH/52 GTY)

120

(60 GTH/60 GTY)

128

(0 GTH/128 GTY)

Total Block RAM






34.6 Mb

34.6 Mb

34.6 Mb

115.2 Mb

132.9 Mb

94.5 Mb

UltraRam, HBM






36 Mb, None

36 Mb, None

36 Mb, None

None, None

None, None

360 Mb, None

Transceiver Speed

 (GTH, GTY)

> 10 Gbit/s

> 10 Gbit/s

> 10 Gbit/s

> 10 Gbit/s

> 10 Gbit/s

GTH 16.3 Gbit/s

GTY 32.75 Gbit/s

Transceivers

GTH 16.3 Gbit/s

GTY 16.3 Gbit/s

Transceivers

GTH 16.3 Gbit/s

GTY 32.75 Gbit/s

Transceivers

GTH 16.3 Gbit/s

GTY 30.5 Gbit/s

Transceivers

GTH 16.3 Gbit/s

GTY 30.5 Gbit/s

Transceivers

GTY 32.75 Gbit/s

Transceivers

Size

The PCB width is (preferably) 65 mm (2.56’’)





42.5 x 42.5 mm

35 x 35 mm

40 x 40 mm

47.5x47.5 mm

52.5 x 52.5 mm

52.5 x 52.5 mm

Cost






6-10 k$

5-9 k$

 6-10k$

40 k$

50-70 k$

60-110 k$

Comments






This is fine for the 2x2 Systems.

This is fine for the SparkPix-S 4x4

The number of GTs in this FPGA does not fit any of the cameras we are targetting

This is fine for the 2x2 Systems.

For the larger systems we need more than 3 FPGAs

This is fine for the 2x2 Systems.

This is fine for the 2x2 Systems (assuming we can fit the real estate).

This is fine for the 2x2 Systems.(assuming we can fit the real estate)

*Done considering 1% Occupancy instead of maxing out the transceivers

Summarizing Table



UHR 2x2SparkPix S 2x2SparkPix S 4x4UHR 5x6UHR 6x6

                              Requirements

Characteristics 

48 GTs48 GTs152 GTs312 GTs360 GTs

KU15P (-A1156) Kintex U+

28 GTs    / 352 mm2       / 10k$❌❌❌❌❌
KU15P (-E1517) Kintex U+56 GTs    / 402 mm2      / 10k$✅✅❌❌❌
KU15P (-A1760) Kintex U+76 GTs    / 42.52 mm2  / 10k$✅✅✅ (2 FPGA)❌❌
XCVU160 (-C2104) Virtex U104 GTs / 47.52  mm2  / 40k$✅✅✅ (2 FPGA)✅ (1 FPGA/module)❌
XCVU190 (- A2577 ) Virtex U120 GTs / 47.52  mm2  / 70k$✅✅✅(2 FPGA)✅ (1 FPGA/module)✅ (1 FPGA/module)
VU13P (-A2577) Virtex U+128 GTs / 52.52  mm2 / 110k$✅✅✅(2 FPGA)✅ (1 FPGA/module)✅ (1 FPGA/module)
Expand
titleFPGA Size Comparison

       

Expand
titleProposed System solutions

ePixUHR 140k 2x2 Detector System

SparkPix S – 500k 2 x 2 ASIC Detector System

Expand
titleUltraScale+ Device Ordering Information

FPGA KU15P (-A1760) Kintex U+ voltage rails

From Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)

NameVoltage
VCCINT0.85 V
VCCINT_IO0.85 V
VCCBRAM0.85 V
VCCAUX1.8 V
VCCAUX_IO1.8 V
MGTVCCAUX_LN/LS/RN/RS1.8 V
VCCADC1.8 V
MGTAVCC_LN/LS/RN/RS0.9 V
MGTAVTT_LN/LS/RN/RS1.2 V
Expand
titleKU15P power estimation

Power calculation SpreadSheet: UltraScalePlus_XPE_2023_140kpx.xlsm


Power

A GUI from Linear Technologies (now Analog Devices) called LTPowerPlanner has been used to calculate all the required currents and voltages in the system. It also calculates the estimated losses and efficiency of the system.

Power block diagramLTPowerPlanner

Gliffy Diagram
size300
displayNamepower-graph
namepower-graph
pagePin106

Board power maps

The figures below give an approximation of where the power is consumed on the readout and ASIC carrier boards. The numbers are from the LTPowerPlanner block diagram above.

Digital board power mapAnalog board power mapePixUHR100k carrier board power mapSparkPix-S carrier board power map

Image Added

Image Added

Image Added

Image Added

DrawIO source file: power-maps.drawio

Power rail current draw

Using worst-case values below for conservative estimate of the currents needed for the different supplies

Digital board

Power supply railPartQuantityMax current
P0V85FPGA VCCINT/VCCINT_IO17 A
Total:7 A
P1V8SN74AXC4T774RSVR33*26 uA = 78 uA
SI5345A-D-GM22*260 mA = 520 mA
FPGA VCCAUX1~500 mA
FPGA VCCAUX_IO1~100 mA
FPGA MGTVCCAUX1~300 mA
FPGA VCCO 01< 100 mA
FPGA XADC_VCC1~10 mA
FPGA VCCO 64/65/66/67/68/70/71/72/911< 100 mA
MT25QU01GBBB8E12-0SIT155 mA
Total:< 1.7 A
P0V9FPGA MGTAVCC14 A
Total:4 A
P1V2FPGA MGTAVTT15.5 A
Total:5.5 A
P3V3SI5345A-D-GM1130 mA
LMK61E2BAA-SIAT22*196 mA = 392 mA
FPGA VCCO 93/941< 50 mA
SN74AHC1G04DBVR33*4 = 12 mA
SN74LVC3G34DCUR3~3*1 = 3 mA
LEAP transceiver12.4 A
Total:< 3 A
P2V5XLL726371.428571I144 mA
536FB156M250DG198 mA
AT24C64D-MAHM-T13 mA
FPGA VCCO 901< 100 mA
DS2411R2< 10 uA
Total:< 0.5 A
P1V3SN74AXC4T774RSVR33*26 uA = 78 uA
Total:< 0.1 A

Analog board

Power supply railPartQuantityMax current (ePixUHR100k)Max current (SparkPix-S)
P1V3_DVDDASIC digital supplies44*0.5*1.2/2 A = 1.2 A4*0.5*1.2/2 A = 1.2 A (preliminary)
Total:< 1.5 A< 1.5 A
P1V3_IOVDDASIC digital supplies44*0.5*1.2/2 A = 1.2 A4*0.5*1.2/2 A = 1.2 A (preliminary)
Total:< 1.5 A< 1.5 A
P3V3DADS1217IPFBT1275 uA
LT3045 for P0V8_DC_BIAS1< 0.1 A
Total:< 0.2 A
P0V8_DC_BIASASIC GT bias4< 0.1 A
Total:< 0.1 A
P1V8DAD9249BBCZ1124 mA
AD5541ABRMZ3< 1 mA
Total:< 0.2 A
P1V3_A1VDDASIC analog supply12.5*1.2 A = 3 A3.15*1.2 = 3.78 A (preliminary)
Total:3 A3.8 A
P1V3_A2VDDASIC analog supply12.5*1.2 A = 3 A3.15*1.2 = 3.78 A (preliminary)
Total:3 A3.8 A
P1V3_A3VDDASIC analog supply12.5*1.2 A = 3 A3.15*1.2 = 3.78 A (preliminary)
Total:3 A3.8 A
P1V3_A4VDDASIC analog supply12.5*1.2 A = 3 A3.15*1.2 = 3.78 A (preliminary)
Total:3 A3.8 A
P3V3AADS1217IPFBT11.325 mA
HIH-5031-00110.5 mA
ADR360BUJZ1< 1 mA
ADR361BUJZ1< 1 mA
OPA2626IDGKR44*2*3.1 mA ≈ 25 mA
AD5541ABRMZ2< 1 mA
MAX4781ETE4< 1 mA
Total:< 0.1 A
P2V5AASIC analog monitors4< 0.1 A
Total:< 0.1 A
P1V8AAD8607ARMZ150 uA
AD9249BBCZ1429 mA
Total:< 0.5 A
P2V5A_SINKLDOs for 0.6 V sink4< 0.5 A
Total:< 0.5 A

← +24 V

The current drawn by the 0.6V current sink should not be counted twice since it's sourced by the G_AS.

The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W.

With 1.8V as the LDO input, we are also burning: (1.8-1.3)V*4.4A*4 = 9W.

The power drawn by the TPS should be less than 2W.

So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W.

Considering the efficiency curves of the DC/DC converters:

34/0.85/0.93 =

43W Total Analog Power

(same calculation for ePixUHR would be 32W)

HS ADC: ~350mA

Slow ADC: few mA

DACs: ~250 mA

Total 0.7A

Worst case scenario starting from 5V,

3.5W/0.85/0.93 = 4.4W

LT3045EDD (LDO)

Max 0.5A
Expand
titleSystem Power Consumption Breakdown
Note

The table below is not up-to-date. Use the LTPowerPlanner above instead

Expand
titleSystem Power Consumption Breakdown
Note

The table below is not up-to-date. Use the LTPowerPlanner above instead

Board

Domain

Part

Final Voltages

Analog

Analog

ASIC

A0VDD_P1V3

1.3V @4.4A

← +1.3V

LT3086 x3 (LDO)

Max 6.3A

← +1.8V (P1V8A_FIRST)

Max 1.8V*6.3A*4 ≈ 45W

LT8638S x2

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10*2 = 20A

(Around 93% efficiency for 24 to 1.8V at max load)

Max 36 W_out, 40 W_in

A1VDD_P1V3

1.3V @4.4A

← +1.3V

LT3086 x3 (LDO)

Max 6.3A

A2VDD_P1V3

1.3V @4.4A

← +1.3V

LT3086 x3 (LDO)

Max 6.3A

A3VDD_P1V3

1.3V @4.4A

← +1.3V

LT3086 x3 (LDO)

Max 6.3A

A0SINK_P0V6

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A

← +2.5V (P2V5_SINK)

LT3086 (LDO)

Max 2.1A

← +5.0V (P5V0A_FIRST)

Max 5.0V*2.1+5.0V*2.1+5.0V*2.1A ≈ 32W

LT8638S

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10A

(Around 93% efficiency for 24 to 5V at max load)

Max 50 W_out, 54 W_in

A1SINK_P0V6

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A

A2SINK_P0V6

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A

A3SINK_P0V6

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A

G_AS_ 2V5

2.5V @ <0.5 A

← +2.5V

LT3086 (LDO)

Max 2.1A

← +5.0V (P5V0A_FIRST)

DAC/ADC/Misc.

P3V3A

+3.3V @ <1A

3.3 W

← +3.3V

LT3086 (LDO)

Max 2.1A

P1V8A

+1.8V @ <1A

1.8 W

← +1.8V

LT3086 (LDO)

Max 2.1A

Digital

ASIC

DVDD_P1V3

1.3V @3A

← +1.3V

LT3086 x2 (LDO)

Max 4.2A

← +1.8V (P1V8D_FIRST)

Max 1.8V*4.2A+1.8V*4.2A+1.8V*2.1A ≈ 20W

LT8638S

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10A

(Around 93% efficiency for 24 to 1.8V at max load)

Max 18 W_out, 19 W_in

← +24 V

For the digital consumption of the ASIC we do not have precise numbers regarding the new logic.

Let's use the old numbers: 1.3V*3A = 4W

While for the I/O voltage we have an expected: 1.3V*2.5A = 3.25 W.

LDO losses: 0.5*5.5 = 2.75 W

10W/0.85/0.93 = 13W (ASIC Digital and I/O)

(same calculation for ePixUHR would be 9.5W)

IOVDD_P1V3

1.3V @3A

← +1.3V

LT3086 x2 (LDO)

Max 4.2A

DAC/ADC/Misc.

P1V8D

+1.8V @ <1A

1.8 W

← +1.8V

LT3086 (LDO)

Max 2.1A

← +5.0V (P5V0D_FIRST)

Max 5.0V*2.1+5.0V*2.1 ≈ 21W

LT8638S

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10A

(Around 93% efficiency for 24 to 5V at max load)

Max 50 W_out, 54 W_in

P3V3D

+3.3V @ <1A

3.3 W

← +3.3V

← +3.3V

LT3086 (LDO)

Max 2.1A

ASIC

P0V8_DC_BIAS

0.8V @0.1A

← +0.8V

Digital Digital0.85V

← +5 V

Max 19*3+42 ≈ 99 W 5V 100 110 ← +2.5V

Board

Domain

Part

Final Voltages








Analog

Analog

FPGA

ASIC

A0VDD_P1V3

1.3V @4.4A

VCCINT

0.85V @7.05 A

6 W

← +

LMZ31520 DC/DC Buck converter

3V to 14.5V input

20A

(Around 90% efficiency)

Max 17 W_out, 19 W_in

1.3V

LT3086 x3 (LDO)

Max 6.3A

← +1.8V (P1V8A_FIRST)

Max 1.8V*6.3A*4 ≈ 45W

LT8638S x2

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10*2 = 20A

(Around 93% efficiency for 24 to

1.8V at max load)

Max

36 W_out,

40 W_in

← +24 V

Total power for FPGA is around: 6+1.3+3.3+6.6≈17W

Considering a worst case efficiency of the DC/DC:
17W/0.85/0.93 = 21.5W (FPGA)

VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX

1.8V @0.7A 

1.3 W

← +1.8V

TPSM5D1806 (DC/DC)
PMIC

4.5V to 15V input

Dual 6A output

(85%  efficiency for max load at Vout = 1.8V)

Max 16 W_out, 19 W_in

MGTAVCC +MGTYAVCC

0.9V @3.7A

3.3 W

← +0.9V

VCC_1.2V + MGTAVTT + MGTYAVTT 

1.2V @5.5A

6.6 W

← +1.2V

TPSM5D1806 (DC/DC)
PMIC

4.5V to 15V input

Parallel 12A output

(Between 80% and 90% efficiency)

Max 15 W_out, 19 W_in

Bank IO, clocks, buffers, etc.

LEAP Transceiver

P3V3

+3.3V @ <4A

13 W

← +3.3V

LT3086 x2 (LDO)

Max 4.2A

← +5V

Max 5V*4.2+5V*2.1A*2 ≈ 42W

LEAP transceiver with everything enable ~8W → 2.4A

Other parts assume < 1A

3.4A * 5V = 17W

17/0.93 ≈ 19W


The current drawn by the 0.6V current sink should not be counted twice since it's sourced by the G_AS.

The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W.

With 1.8V as the LDO input, we are also burning: (1.8-1.3)V*4.4A*4 = 9W.

The power drawn by the TPS should be less than 2W.


So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W.

Considering the efficiency curves of the DC/DC converters:

34/0.85/0.93 =

43W Total Analog Power

(same calculation for ePixUHR would be 32W)

A1VDD_P1V3

1.3V @4.4A

← +1.3V

LT3086 x3 (LDO)

Max 6.3A

A2VDD_P1V3

1.3V @4.4A

← +1.3V

LT3086 x3 (LDO)

Max 6.3A

A3VDD_P1V3

1.3V @4.4A

← +1.3V

LT3086 x3 (LDO)

Max 6.3A

A0SINK_P0V6

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A

← +2.5V (P2V5_SINK)

Bank IO, clocks, buffers, etc.

P2V5

+2.5V @ <1A

2.5 W

LT3086 (LDO)

Max 2.1A

ASIC IO level translators

P1V3

+1.3V @ <10mA

<0.1 W

← +1.3V

LT3086 (LDO)

Max 2.1A

DC/DC converters

Product number

Type

Input Voltage

Output Voltage

Max Current

Comment

LT8638S Buck2.8V to 42V0.6V to 42V10ADC/DC Step Down converter. Parallel operation possible.
(same as used in Power & communication board (PC_261_101_26_C00) TPSM5D1806 Buck4.5V to 15V0.5V to 5.5VDual 6A / Single 12A DC/DC PMIC LMZ31520 Buck3V to 14.5V0.6V to 3.6V20ADC/DC Buck converter. 30A version LMZ31530. LT3086 LDO1.4V to 40V0.4V to 32V2.1ALow Output Noise: 40µVRMS (10Hz to 100kHz). Parallel operation possible. LT3091 LDO–1.5V to –36V0V to –32V-1.5A

Negative Linear Regulator. Low Output Noise: 18µVRMS (10Hz to 100kHz). Parallel operation possible.

Texas Instruments WEBENCH

https://webench.ti.com/power-designer/switching-regulator

LMZ31520 - digital board - 5.0 V to 0.85 V

Image Removed

TPSM5D1806 - digital board - 5.0 V to 1.8 V and 0.9 V

Image Removed

TPSM5D1806 - digital board - 5.0 V to 1.2 V

Image Removed

Optional bypass of LDOs for ASIC

There are optional bypass jumpers on the analog board, as shown in the diagram above, for providing power to the ASIC directly from the LT8638S switching regulators. This will bypass the LDOs and can be used to test the performance of the ASIC when it's powered from a "dirtier" power source.

Warning
titleWarning if bypassing LDOs for ASICs

Make sure to adjust the output voltage of the switching regulators from 1.8 V to 1.3 V before powering up with an ASIC as the 1.8 V can cause permanent damage! The LDOs that are bypassed should also be removed from the board.

Paralleling of DC/DC and LDOs from data sheets

Gliffy Diagram
size300
displayNamepower-parallel-circuits
namepower-parallel-circuits
pagePin1

Expand
titleePixUHR 140k 2x2 Power Graph

OLD Graph:

Image Removed

System level

RequirementParametersNotesPower supply24 V consistent with the HR detectorMechanical size

We would like to match the ePixHRM board dimensions to reuse cooling

Side entrance detector

  • Existing 75 x 175 mm x 58:
  • max envelope would be (100 x 175 x 75 mm)

Image Removed

Digital board2.56 x 5.265"Power and communication2.56 x 5.240"Carrier

2.56 x 1.95"

  • Can we do it smaller?
  • What is the minimum amount of components that need to leave in this board?

General I/O

Expand
titleGeneral IOs for the 2x2(numbers based on ePixHR250M)

ePixUHR Signals (single ASIC)

N# Pins

Power Digital Signals

N# Pins

Digital Core Signals

N# Pins

P&CB Signals

N# Pins

Waveform/ ASIC Ctrl

5

LDO enables

7

Env. Monitors

7

Misce

24

Clk

2 (0 if also clk_matrix is sent via GT)

DCDC Syncs

2

Bias DAC

4

Spare

6

Slow Ctrl (SACI/Sugoi)

4

HS DAC

4

Digital Monitor

2

HS ADC

6+24+8 =38

Miscellan

5

Jitter Cleaner

12

Total

13

Total

9

Total

70

Total

30

TOTAL = 13 * 4( n.Asics ) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP

Expand
titleIO

For single ended → check the electrical specification

Image Removed

Other components

Component

Product number

Board

Voltage

Power consumption

Comments

Quad SPI Configuration Memory

MT25QU01GBBB8E12

Digital

1.8V

Max 50mA

EEPROM

24LC32A-I/MS

Digital

2.5V

1mA

JTAG

Digital

1.8V

Analog Monitor (SlowADC) ADC

ADS1217

Both (key at the analog board, optional at the digital board)

AVDD=3.3V

DVDD=1.8V

< 1mA

Maybe. The datasheet guarantees operation for digital down to 2.7V,  in HR250 was put at 1.8. Check if it is fine!

Analog Monitor MUX (x5)

MAX4734

may be needed depending on the number of channels we decide to monitor (all voltages and currents to the ASIC, humidity,...)

AVDD=3.3V

< 1uA

They are controlled by the ADC

Humidity sensor

HIH_5031_001

Analog

3.3V

No

Thermistor

NTC_NHQM103B375T10

Carrier

No

Oscillators

•371 MHz XLL726371.428571I

•156 MHz 536FB156M250DG

•48 MHz CX3225SB48000D0FPJC1

Digital

2.5V

Both 1.8V and 2.5V solutions can be found depending on the voltage we want to use

Clock Fanout

SI53340-B-GM

Digital

3.3V

Clock Jitter cleaner

SI5345_64QFN

Digital

VDD=3.3V

DVDD=1.8V

Programmable Oscillator

LMK61E2

Digital

3.3V

Used?

High Speed ADC

AD9249

Analog

1.8V

Max 58mW/channel:

58*12 = 700mW

No

ADC_MON_VCM Buffer

AD8607_MSO8

Analog

1.8V

Bias DAC (HV Ring)

MAX5443 (DAC) +

MAX14611 (Level Shifter) +

REF192GS  (Voltage reference)

Analog

3.0 V (VCCA)

Needed? Will the sensors have an HV ring?

ASIC clk fanout

SI53340-B-GM

Analog???

Probably not needed

HS DAC (Vcalib_p)

AD5541A (DAC)

+OPA2626(Buffer)

+ADR360B(Vref)

VDD = 3/3.3V

VLogic = 1.8V

Vref = 2V

Level shifters for ASCI SACI interfacing

MAX3378EEUD+

Digital

1.3V -> 1.8V

Level Shifter for Power controllers

MAX3378EETD (x2)

MAX3373E_SOT23_8 (x1)

to be defined

???

Serial number

DS2411R

Carrier, analog and digital boards

All at 2.5V provided from the digital board

Line Equalizer

(check the one used for cryo)

Analog

Nice to have

Transceiver

  • Ideal is to reuse the 300 Gbit/s Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode fiber optics.
  • Amphenol Transceivers Product Presentation
  • About the stock (at 12 December 2023):
    • interconnect that is soldered on the board we have in stock :
    • 10140369-201LF (qty.25)
    • 10140369-101LF (qty.4)

    • (I checked the parts and both of them say -101LF on the component. 201 is different only on the numbering on the label. So in total we have 29)

    • Laser transceiver part:
      10124588-410 (no heatsink) (qty.5)
      10124588-411 (low profile heatsink)(qty.15)
      (Online you cannot find description of -410 and -411. I am pretty sure they are equivalent to the -310 and -311) 
    • Optical cable:
      Needs to be custom ordered

Board material 

  • Needs to be FR408HR or better
AnchorconnectorsconnectorsConnectorsFunctionalityObservationslinkCarrier to analog board
  • How are we going to prevent ePixHRM carriers to be connected in to the 100kfps digital board and vice-versa?
    • Options could be mechanical pins or change connector polarities
    • Or via serial ID (needs to have a database) via soft locks
  • Routes all power, data and control signals to/from the ASICs
https://docs.google.com/spreadsheets/d/1b_nFUIKPOlVZJwAgv-RxHJQhuoHP3wuV?rtpof=true&usp=drive_fsAnalog to digital board
  • Distributes the 24V from the power connector
  • Routes data and control signals between the ASIC on the carrier and the FPGA on the digital board
External power supply
  • Should be on the bottom board (digital) because a pigtail is connected to it that is attached to the outside shell
    • If if was on the top board (analog) there's a risk of damaging the ASICs and their wirebonds on the carrier
Optical transceiver
  • Same as for the power connector
  • Place close to FPGA due to 25 Gbit/s signals

Gliffy Diagram
size600
displayNameconnector-sideview
nameconnector-sideview
pagePin19

Expand
titleArchive

Image Removed

Cooling block

Current cooling blockUpdated cooling block

The photo below shows the current cooling block designs (straight and angled), which is for a 30x6 SEAM/SEAF connector between analog and digital board.

The screenshot below shows that a 40x8 SEAM/SEAF connector can fit by extending the cutout in the cooling block without interfering with the pipe. Orange lines are the outline of the cooling block and the pipes in it.

The new connector is 10*1.27 = 12.7 mm longer.

Image Removed

Image Removed

AnchorgroundinggroundingGrounding
  • Separate ground come into the system through the TFM power connector on the digital board
  • The HV supply ground and the Analog supply ground are connected to the same analog ground net
  • The digital supply is connected to the digital ground net
  • The analog and digital grounds are connected together on the digital board near the TFM power connector

Gliffy Diagram
macroId9e4248c4-2fd4-4aca-81b6-2eb6b5355399
displayNamegrounding-diagram
namegrounding-diagram
pagePin10

Clocks

There are four main clock sources:

  • Oscillator for GTY transceivers for LCLS-II timing
  • Oscillator for GTY transceivers for PGP communication
  • Jitter attenuator with various input choices for FPGA logic and GTY transceivers
  • Jitter attenuator with various input choices for FPGA logic and GTH transceivers

The SI53340 clock buffer only buffers the input clock source into four output clocks with low amount of jitter added. The SI5345B is a jitter attenuator and an "any-frequency" multiplier where one input is selected that is fed to a PLL which then feeds multipliers for the individual outputs. Each output can therefore be programmed to different frequencies, which are synchronous with the selected input clock.

Clock structure diagram

Gliffy Diagram
macroIdb2f59737-11bc-4242-aa9a-3b5eea4fd1e1
displayNameclock-structure
nameclock-structure
pagePin35

ASIC GT clock generation

The gigabit transceivers (GTs) in the ASIC require a high-frequency clock (2-3 GHz) with low jitter. There is no PLL inside the ASIC so it has to be provided from an external source (see SparkPix-IOs: fast I/Os prototype (~5 Gb/s) on TSMC 130nm). The proposed architecture will use the GTH transceiver outputs of the Kintex UltraScale+ to generate a "clock" from a static "101010..." bit pattern.

Gliffy Diagram
displayNameasic-gt-clocking
nameasic-gt-clocking
pagePin4

ASIC GT AC-coupling

There are high-speed signals in both directions between the ASICs and the FPGA:

  • Clock signals from the FPGA GTH TX to the ASIC GT CLK
  • Data signals from the ASIC GT TX to the FPGA GTH RX

These could either be DC-coupled or AC-coupled, which means that a series capacitor in the order of ~100nF is placed in series with the signal somewhere along the path. It is also called DC-blocking capacitors as described by Dr. Howard Johnson in an article on his website. The question is, where to place the capacitors? Close to the transmitter, in the middle, close to the receiver or somewhere else? In Johnson's article he argues that the main effect of these capacitors will be an impedance mismatch because the package of the capacitor will be bigger than the trace itself and we end up with an impedance that is less than the nominal impedance Z0 of the transmission line. This will result in negative reflections. He then argues that the effect of such a reflection has to be considered in relationship to the symbol baud interval and if it's much less than 1/2 of the baud interval it will have a minimal effect. We are working with up to 6 Gbit/s which gives a baud interval of 167ps. With a propagation delay of around 150 ps/inch (source) it means that to have minimal impact it has to be much less than 1/4 inch (~6 mm), somewhere in the order 1/20 of an inch (~1.2 mm) which is not practical on a PCB with IC packages, passives and routing.

← +5.0V (P5V0A_FIRST)

Max 5.0V*2.1+5.0V*2.1+5.0V*2.1A ≈ 32W

LT8638S

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10A

(Around 93% efficiency for 24 to 5V at max load)

Max 50 W_out, 54 W_in

HS ADC: ~350mA

Slow ADC: few mA

DACs: ~250 mA

Total 0.7A

Worst case scenario starting from 5V,

3.5W/0.85/0.93 = 4.4W



A1SINK_P0V6

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A

A2SINK_P0V6

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A

A3SINK_P0V6

0.6V @ -2.75A

← +0.6V

LT3091 x2 (LDO)

Max 3.0A

G_AS_ 2V5

2.5V @ <0.5 A

← +2.5V

LT3086 (LDO)

Max 2.1A

← +5.0V (P5V0A_FIRST)

DAC/ADC/Misc.

P3V3A

+3.3V @ <1A

3.3 W

← +3.3V

LT3086 (LDO)

Max 2.1A

P1V8A

+1.8V @ <1A

1.8 W

← +1.8V

LT3086 (LDO)

Max 2.1A

Digital

ASIC

DVDD_P1V3

1.3V @3A

← +1.3V

LT3086 x2 (LDO)

Max 4.2A

← +1.8V (P1V8D_FIRST)

Max 1.8V*4.2A+1.8V*4.2A+1.8V*2.1A ≈ 20W

LT8638S

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10A

(Around 93% efficiency for 24 to 1.8V at max load)

Max 18 W_out, 19 W_in

← +24 V

For the digital consumption of the ASIC we do not have precise numbers regarding the new logic.

Let's use the old numbers: 1.3V*3A = 4W

While for the I/O voltage we have an expected: 1.3V*2.5A = 3.25 W.

LDO losses: 0.5*5.5 = 2.75 W

10W/0.85/0.93 = 13W (ASIC Digital and I/O)

(same calculation for ePixUHR would be 9.5W)

IOVDD_P1V3

1.3V @3A

← +1.3V

LT3086 x2 (LDO)

Max 4.2A

DAC/ADC/Misc.

P1V8D

+1.8V @ <1A

1.8 W

← +1.8V

LT3086 (LDO)

Max 2.1A

← +5.0V (P5V0D_FIRST)

Max 5.0V*2.1+5.0V*2.1 ≈ 21W

LT8638S

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10A

(Around 93% efficiency for 24 to 5V at max load)

Max 50 W_out, 54 W_in

P3V3D

+3.3V @ <1A

3.3 W

← +3.3V

← +3.3V

LT3086 (LDO)

Max 2.1A

ASIC

P0V8_DC_BIAS

0.8V @0.1A

← +0.8V

LT3045EDD (LDO)

Max 0.5A

Board

Domain

Part

Final Voltages








Digital

Digital

FPGA

VCCINT

0.85V @7.05 A

6 W

← +0.85V

LMZ31520 DC/DC Buck converter

3V to 14.5V input

20A

(Around 90% efficiency)

Max 17 W_out, 19 W_in

← +5 V

Max 19*3+42 ≈ 99 W

LT8638S x2

42V, 10A Synchronous Step-Down Silent Switcher 2

Max Current = 10*2 = 20A

(Around 93% efficiency for 24 to 5V at max load)

Max 100 W_out, 110 W_in

← +24 V

Total power for FPGA is around: 6+1.3+3.3+6.6≈17W

Considering a worst case efficiency of the DC/DC:
17W/0.85/0.93 = 21.5W (FPGA)

VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX

1.8V @0.7A 

1.3 W

← +1.8V

TPSM5D1806 (DC/DC)
PMIC

4.5V to 15V input

Dual 6A output

(85%  efficiency for max load at Vout = 1.8V)

Max 16 W_out, 19 W_in

MGTAVCC +MGTYAVCC

0.9V @3.7A

3.3 W

← +0.9V

VCC_1.2V + MGTAVTT + MGTYAVTT 

1.2V @5.5A

6.6 W

← +1.2V

TPSM5D1806 (DC/DC)
PMIC

4.5V to 15V input

Parallel 12A output

(Between 80% and 90% efficiency)

Max 15 W_out, 19 W_in

Bank IO, clocks, buffers, etc.

LEAP Transceiver

P3V3

+3.3V @ <4A

13 W

← +3.3V

LT3086 x2 (LDO)

Max 4.2A

← +5V

Max 5V*4.2+5V*2.1A*2 ≈ 42W

LEAP transceiver with everything enable ~8W → 2.4A

Other parts assume < 1A

3.4A * 5V = 17W

17/0.93 ≈ 19W

Bank IO, clocks, buffers, etc.

P2V5

+2.5V @ <1A

2.5 W

← +2.5V

LT3086 (LDO)

Max 2.1A


ASIC IO level translators

P1V3

+1.3V @ <10mA

<0.1 W

← +1.3V

LT3086 (LDO)

Max 2.1A

DC/DC converters

Product number

Type

Input Voltage

Output Voltage

Max Current

Comment

LT8638S Buck2.8V to 42V0.6V to 42V10ADC/DC Step Down converter. Parallel operation possible.
(same as used in Power & communication board (PC_261_101_26_C00)
TPSM5D1806 Buck4.5V to 15V0.5V to 5.5VDual 6A / Single 12A DC/DC PMIC
LMZ31520 Buck3V to 14.5V0.6V to 3.6V20ADC/DC Buck converter. 30A version LMZ31530.
LT3086 LDO1.4V to 40V0.4V to 32V2.1ALow Output Noise: 40µVRMS (10Hz to 100kHz). Parallel operation possible.
LT3091 LDO–1.5V to –36V0V to –32V-1.5A

Negative Linear Regulator. Low Output Noise: 18µVRMS (10Hz to 100kHz). Parallel operation possible.

Texas Instruments WEBENCH

https://webench.ti.com/power-designer/switching-regulator

LMZ31520 - digital board - 5.0 V to 0.85 V

Image Added

TPSM5D1806 - digital board - 5.0 V to 1.8 V and 0.9 V

Image Added

TPSM5D1806 - digital board - 5.0 V to 1.2 V

Image Added

Optional bypass of LDOs for ASIC

There are optional bypass jumpers on the analog board, as shown in the diagram above, for providing power to the ASIC directly from the LT8638S switching regulators. This will bypass the LDOs and can be used to test the performance of the ASIC when it's powered from a "dirtier" power source.

Warning
titleWarning if bypassing LDOs for ASICs

Make sure to adjust the output voltage of the switching regulators from 1.8 V to 1.3 V before powering up with an ASIC as the 1.8 V can cause permanent damage! The LDOs that are bypassed should also be removed from the board.

Paralleling of DC/DC and LDOs from data sheets

Gliffy Diagram
size300
displayNamepower-parallel-circuits
namepower-parallel-circuits
pagePin1

Expand
titleePixUHR 140k 2x2 Power Graph

OLD Graph:

Image Added

System level

RequirementParametersNotes
Power supply24 V consistent with the HR detector
Mechanical size

We would like to match the ePixHRM board dimensions to reuse cooling

Side entrance detector

  • Existing 75 x 175 mm x 58:
  • max envelope would be (100 x 175 x 75 mm)

Image Added

Digital board2.56 x 5.265"
Power and communication2.56 x 5.240"
Carrier

2.56 x 1.95"


  • Can we do it smaller?
  • What is the minimum amount of components that need to leave in this board?

General I/O

Expand
titleGeneral IOs for the 2x2(numbers based on ePixHR250M)

ePixUHR Signals (single ASIC)

N# Pins


Power Digital Signals

N# Pins


Digital Core Signals

N# Pins


P&CB Signals

N# Pins

Waveform/ ASIC Ctrl

5


LDO enables

7


Env. Monitors

7


Misce

24

Clk

2 (0 if also clk_matrix is sent via GT)


DCDC Syncs

2


Bias DAC

4


Spare

6

Slow Ctrl (SACI/Sugoi)

4





HS DAC

4




Digital Monitor

2





HS ADC

6+24+8 =38










Miscellan

5










Jitter Cleaner

12




Total

13


Total

9


Total

70


Total

30

TOTAL = 13 * 4( n.Asics ) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP

Expand
titleIO

For single ended → check the electrical specification

Image Added

Other components

Expand

Component

Product number

Board

Voltage

Power consumption

Comments

Quad SPI Configuration Memory

MT25QU01GBBB8E12

Digital

1.8V

Max 50mA


EEPROM

24LC32A-I/MS

Digital

2.5V

1mA


JTAG


Digital

1.8V



Analog Monitor (SlowADC) ADC

ADS1217

Both (key at the analog board, optional at the digital board)

AVDD=3.3V

DVDD=1.8V

< 1mA

Maybe. The datasheet guarantees operation for digital down to 2.7V,  in HR250 was put at 1.8. Check if it is fine!

Analog Monitor MUX (x5)

MAX4734

may be needed depending on the number of channels we decide to monitor (all voltages and currents to the ASIC, humidity,...)

AVDD=3.3V

< 1uA

They are controlled by the ADC

Humidity sensor

HIH_5031_001

Analog

3.3V


No

Thermistor

NTC_NHQM103B375T10

Carrier

No

Oscillators

•371 MHz XLL726371.428571I

•156 MHz 536FB156M250DG

•48 MHz CX3225SB48000D0FPJC1

Digital

2.5V


Both 1.8V and 2.5V solutions can be found depending on the voltage we want to use

Clock Fanout

SI53340-B-GM

Digital

3.3V



Clock Jitter cleaner

SI5345_64QFN

Digital

VDD=3.3V

DVDD=1.8V



Programmable Oscillator

LMK61E2

Digital

3.3V


Used?


High Speed ADC

AD9249

Analog

1.8V

Max 58mW/channel:

58*12 = 700mW

No

ADC_MON_VCM Buffer

AD8607_MSO8

Analog

1.8V



Bias DAC (HV Ring)

MAX5443 (DAC) +

MAX14611 (Level Shifter) +

REF192GS  (Voltage reference)

Analog

3.0 V (VCCA)


Needed? Will the sensors have an HV ring?

ASIC clk fanout

SI53340-B-GM

Analog???

Probably not needed

HS DAC (Vcalib_p)

AD5541A (DAC)

+OPA2626(Buffer)

+ADR360B(Vref)


VDD = 3/3.3V

VLogic = 1.8V

Vref = 2V



Level shifters for ASCI SACI interfacing

MAX3378EEUD+

Digital

1.3V -> 1.8V



Level Shifter for Power controllers

MAX3378EETD (x2)

MAX3373E_SOT23_8 (x1)

to be defined

???



Serial number

DS2411R

Carrier, analog and digital boards

All at 2.5V provided from the digital board



Line Equalizer

(check the one used for cryo)

Analog



Nice to have

Transceiver

  • Ideal is to reuse the 300 Gbit/s Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode fiber optics.
  • Amphenol Transceivers Product Presentation
  • About the stock (at 12 December 2023):
    • interconnect that is soldered on the board we have in stock :
    • 10140369-201LF (qty.25)
    • 10140369-101LF (qty.4)
    • (I checked the parts and both of them say -101LF on the component. 201 is different only on the numbering on the label. So in total we have 29)
    • Laser transceiver part:
      • 10124588-410 (no heatsink) (qty.5)
      • 10124588-411 (low profile heatsink)(qty.15)
      • (Online you cannot find description of -410 and -411. I am pretty sure they are equivalent to the -310 and -311) 
    • Optical cable: Needs to be custom ordered

Anchor
connectors
connectors
Connectors

FunctionalityObservationslink
Carrier to analog board
  • How are we going to prevent ePixHRM carriers to be connected in to the 100kfps digital board and vice-versa?
    • Options could be mechanical pins or change connector polarities
    • Or via serial ID (needs to have a database) via soft locks
  • Routes all power, data and control signals to/from the ASICs
https://docs.google.com/spreadsheets/d/1b_nFUIKPOlVZJwAgv-RxHJQhuoHP3wuV?rtpof=true&usp=drive_fs
Analog to digital board
  • Distributes the 24V from the power connector
  • Routes data and control signals between the ASIC on the carrier and the FPGA on the digital board
External power supply
  • Should be on the bottom board (digital) because a pigtail is connected to it that is attached to the outside shell
    • If if was on the top board (analog) there's a risk of damaging the ASICs and their wirebonds on the carrier

Optical transceiver
  • Same as for the power connector
  • Place close to FPGA due to 25 Gbit/s signals

Gliffy Diagram
size600
displayNameconnector-sideview
nameconnector-sideview
pagePin19

Expand
titleArchive

Image Added

Cooling block

See

Jira
serverSLAC National Accelerator Laboratory
serverId1b8dc293-975d-3f2d-b988-18fd9aec1546
keyTIDIDECS-180

Current cooling blockUpdated cooling block

The photo below shows the current cooling block designs (straight and angled), which is for a 30x6 SEAM/SEAF connector between analog and digital board.

The screenshot below shows that a 40x8 SEAM/SEAF connector can fit by extending the cutout in the cooling block without interfering with the pipe. Orange lines are the outline of the cooling block and the pipes in it.

The new connector is 10*1.27 = 12.7 mm longer.

Image Added

Image Added

Team center

DSG-000074563*

DSG-000074553

Anchor
grounding
grounding
Grounding

  • Separate ground come into the system through the TFM power connector on the digital board
  • The HV supply ground and the Analog supply ground are connected to the same analog ground net
  • The digital supply is connected to the digital ground net
  • The analog and digital grounds are connected together on the digital board near the TFM power connector

Gliffy Diagram
macroId9e4248c4-2fd4-4aca-81b6-2eb6b5355399
displayNamegrounding-diagram
namegrounding-diagram
pagePin10

Clocks

There are four main clock sources:

  • Oscillator for GTY transceivers for LCLS-II timing
  • Oscillator for GTY transceivers for PGP communication
  • Jitter attenuator with various input choices for FPGA logic and GTY transceivers
  • Jitter attenuator with various input choices for FPGA logic and GTH transceivers

The SI53340 clock buffer only buffers the input clock source into four output clocks with low amount of jitter added. The SI5345B is a jitter attenuator and an "any-frequency" multiplier where one input is selected that is fed to a PLL which then feeds multipliers for the individual outputs. Each output can therefore be programmed to different frequencies, which are synchronous with the selected input clock.

Clock structure diagram

Gliffy Diagram
macroIdb2f59737-11bc-4242-aa9a-3b5eea4fd1e1
displayNameclock-structure
nameclock-structure
pagePin36

ASIC GT clock generation

The gigabit transceivers (GTs) in the ASIC require a high-frequency clock (2-3 GHz) with low jitter. There is no PLL inside the ASIC so it has to be provided from an external source (see SparkPix-IOs: fast I/Os prototype (~5 Gb/s) on TSMC 130nm). The proposed architecture will use the GTH transceiver outputs of the Kintex UltraScale+ to generate a "clock" from a static "101010..." bit pattern.

Gliffy Diagram
displayNameasic-gt-clocking
nameasic-gt-clocking
pagePin4

ASIC GT AC-coupling

There are high-speed signals in both directions between the ASICs and the FPGA:

  • Clock signals from the FPGA GTH TX to the ASIC GT CLK
  • Data signals from the ASIC GT TX to the FPGA GTH RX

These could either be DC-coupled or AC-coupled, which means that a series capacitor in the order of ~100nF is placed in series with the signal somewhere along the path. It is also called DC-blocking capacitors as described by Dr. Howard Johnson in an article on his website. The question is, where to place the capacitors? Close to the transmitter, in the middle, close to the receiver or somewhere else? In Johnson's article he argues that the main effect of these capacitors will be an impedance mismatch because the package of the capacitor will be bigger than the trace itself and we end up with an impedance that is less than the nominal impedance Z0 of the transmission line. This will result in negative reflections. He then argues that the effect of such a reflection has to be considered in relationship to the symbol baud interval and if it's much less than 1/2 of the baud interval it will have a minimal effect. We are working with up to 6 Gbit/s which gives a baud interval of 167ps. With a propagation delay of around 150 ps/inch (source) it means that to have minimal impact it has to be much less than 1/4 inch (~6 mm), somewhere in the order 1/20 of an inch (~1.2 mm) which is not practical on a PCB with IC packages, passives and routing.

For these high-speed cases it is therefore not the distance of the capacitor from the transmitter that matters, but instead the layout and routing of the traces around the capacitor.The goal is instead to minimize the effect of the capacitor on the impedance of the trace. One example Johnson gives is to reduce the parasitic capacitance underneath the body of the capacitor with a keep-out region in the reference plane underneath. A similar concept is shown in a layout design guide (local pdf copy, see page 30) for an Intel Stratix 10 device.

If we look at the LEAP transceiver that we are using in this project we can see that it has the AC-coupling capacitors on both RX and TX inside the package itself. This probably ensures that the effect of the capacitors is reduced as much as possible and they might use very small package sizes.

In our case it's probably a question of physical constraints that define where we can place the capacitors. For all four ASICs we would need 4*8*2+4*2=72 capacitors for data and clocks. Placing these on the carrier board might be tricky. Having them on the analog board would be a tight fit due to all the power supplies it has. That leaves the digital board which should hopefully have enough space to make a "clean" implementation of these capacitors.

ASIC timing and control signals - voltage level translation

The ASIC timing (SRO, R0, ACQ and INJ) and control (GR_N, SACI_SEL[3..0], SACI_CLK, SACI_CMD and SACI_RSP) are 1.3 V CMOS signals in the ASIC that has be be interfaced with the FPGA banks. In previous systems (e.g. ePixHR10k 2M digital board (TXI)) these were 2.5 V CMOS and were driven directly from HD banks in the Kintex UltraScale+ (except for SACI_SEL and SACI_RSP that were driven via MAX3002 from 1.8 V HP banks).

In short, there are two types of voltage level translators: auto-sensing bidirectional ones with transmission gates that will pull up or down when a rising or falling edge are detected; directional ones which has input receivers in one voltage domain and output drivers in the other voltage domain. The auto-sensing ones seem to lack information about the timing characteristics in the datasheet which is probably because it depends on how it is used and the device that is driving the pins of the translator. The directional ones are probably a better fit for this application where we know the direction and want as high drive strength as possible to propagate from the digital board all the way to the ASIC on the carrier board.

FPGA HD banks

FPGA HP banks

MAX3002MAX3378ETI AXC seriesTI TXU seriesTI TXV series

From DS922 datasheet:

  • LVCMOS12 - supported drive strengths of 4, 8, or 12 mA
  • LVCMOS25 - supported drive strengths of 4, 8, 12, or 16 mA

From DS922 datasheet:

  • LVCMOS12 - Supported drive strengths of 2, 4, 6, or 8 mA
  • LVCMOS18 - Supported drive strengths of 2, 4, 6, 8, or 12 mA

This was used on the previous TXI digital board.

  • Auto-sensing bidirectional
  • Product page: https://www.analog.com/en/products/max3002.html

  • Operation down to +1.2 V on V L

  • No data on drive strength provided in data sheet
    • It only has graphs of "rise/fall time vs. capacitive load" for VCC=3.3 V / VL=1.8 V

This was originally used in this design before the schematic review.

  • Auto-sensing bidirectional
  • Product page: https://www.analog.com/en/products/max3378e.html
  • Operation down to +1.2 V on VL
  • No data on drive strength provided in data sheet
    • It only has graphs of "rise/fall time vs. capacitive load" for VCC=3.3 V / VL=1.8 V and VCC=2.5 V / VL=1.8 V

Resources


Anchor
board-design
board-design
Board design

For these high-speed cases it is therefore not the distance of the capacitor from the transmitter that matters, but instead the layout and routing of the traces around the capacitor.The goal is instead to minimize the effect of the capacitor on the impedance of the trace. One example Johnson gives is to reduce the parasitic capacitance underneath the body of the capacitor with a keep-out region in the reference plane underneath. A similar concept is shown in a layout design guide (local pdf copy, see page 30) for an Intel Stratix 10 device.

If we look at the LEAP transceiver that we are using in this project we can see that it has the AC-coupling capacitors on both RX and TX inside the package itself. This probably ensures that the effect of the capacitors is reduced as much as possible and they might use very small package sizes.

In our case it's probably a question of physical constraints that define where we can place the capacitors. For all four ASICs we would need 4*8*2+4*2=72 capacitors for data and clocks. Placing these on the carrier board might be tricky. Having them on the analog board would be a tight fit due to all the power supplies it has. That leaves the digital board which should hopefully have enough space to make a "clean" implementation of these capacitors.

ASIC timing and control signals - voltage level translation

The ASIC timing (SRO, R0, ACQ and INJ) and control (GR_N, SACI_SEL[3..0], SACI_CLK, SACI_CMD and SACI_RSP) are 1.3 V CMOS signals in the ASIC that has be be interfaced with the FPGA banks. In previous systems (e.g. ePixHR10k 2M digital board (TXI)) these were 2.5 V CMOS and were driven directly from HD banks in the Kintex UltraScale+ (except for SACI_SEL and SACI_RSP that were driven via MAX3002 from 1.8 V HP banks).

In short, there are two types of voltage level translators: auto-sensing bidirectional ones with transmission gates that will pull up or down when a rising or falling edge are detected; directional ones which has input receivers in one voltage domain and output drivers in the other voltage domain. The auto-sensing ones seem to lack information about the timing characteristics in the datasheet which is probably because it depends on how it is used and the device that is driving the pins of the translator. The directional ones are probably a better fit for this application where we know the direction and want as high drive strength as possible to propagate from the digital board all the way to the ASIC on the carrier board.

FPGA HD banks

FPGA HP banks

MAX3002MAX3378ETI AXC seriesTI TXU seriesTI TXV series

From DS922 datasheet:

  • LVCMOS12 - supported drive strengths of 4, 8, or 12 mA
  • LVCMOS25 - supported drive strengths of 4, 8, 12, or 16 mA

From DS922 datasheet:

  • LVCMOS12 - Supported drive strengths of 2, 4, 6, or 8 mA
  • LVCMOS18 - Supported drive strengths of 2, 4, 6, 8, or 12 mA

This was used on the previous TXI digital board.

  • Auto-sensing bidirectional
  • Product page: https://www.analog.com/en/products/max3002.html

  • Operation down to +1.2 V on V L

  • No data on drive strength provided in data sheet
    • It only has graphs of "rise/fall time vs. capacitive load" for VCC=3.3 V / VL=1.8 V

This was originally used in this design before the schematic review.

  • Auto-sensing bidirectional
  • Product page: https://www.analog.com/en/products/max3378e.html
  • Operation down to +1.2 V on VL
  • No data on drive strength provided in data sheet
    • It only has graphs of "rise/fall time vs. capacitive load" for VCC=3.3 V / VL=1.8 V and VCC=2.5 V / VL=1.8 V

Resources

Anchorboard-designboard-designBoard design

Altium 365 project folder: https://stanford-linear-accelerator-center.365.altium.com/designs/folder-077F97F3-88BC-43E1-A2A7-66F200D82CFA

Multi-board project

GT-Readout-Platform-template

Digital Board

GT-Readout-Platform-digital

Analog Board

GT-Readout-Platform-analog

Carrier Template Board

GT-Readout-Platform-carrier-template

3D view

Image Removed

Image Removed

Image Removed

Image Removed

DescriptionTemplate multi-board project with the three boards on the right connected togheter.

Digital board for the GT Readout Platform with FPGA and optical transceivers

Analog board for the GT Readout Platform with power supplies, monitoring and calibration circuit for the ASIC carrier board that plugs into it

Template board for ASICs that plugs into the analog board in the GT Readout Platform

Altium 365 projecthttps://stanford-linear-accelerator-center.365.altium.com/designs/5186839B-3CA3-4D54-8947-817E5400B729https://stanford-linear-accelerator-center.365.altium.com/designs/15351422-ADCD-4239-875B-3D8D5E0BD347https://stanford-linear-accelerator-center.365.altium.com/designs/40A8ABB0-467C-443B-B76D-D732550EB38Ahttps://stanford-linear-accelerator-center.365.altium.com/designs/AE5F4BFE-DBC6-4B3C-9281-8A1FBAC9D0BABoard trackingGT Readout ASICsPC_261_101_38_C00PC_261_101_39_C00PC_261_101_40_C00

ePixUHR100k 2x2 implementation

Multi-board projectCarrier Board3D view

Image Removed

Image Removed

DescriptionA configuration of the GT Readout Platform with a 2x2 carrier of ePixUHR100k ASICs.Carrier board for a 2x2 configuration of ePixUHR100k ASICs for use with the GT Readout PlatformAltium 365 projecthttps://stanford-linear-accelerator-center.365.altium.com/designs/C336DBA6-5DE8-4D97-A0B7-201D360144ADhttps://stanford-linear-accelerator-center.365.altium.com/designs/A5E77218-0D70-48E0-A796-5AAAA2E44FDDBoard trackingGT Readout ASICsPC_261_101_41_C00

ePixUHR100k 1x4 implementation

Multi-board projectCarrier Board3D view

Image Removed

Image Removed

DescriptionA configuration of the GT Readout Platform with a 1x4 and 4x1 carrier of ePixUHR100k ASICs.Carrier board for a 1x4 configuration of ePixUHR100k ASICs for use with the GT Readout PlatformAltium 365 projecthttps://stanford-linear-accelerator-center.365.altium.com/designs/32095811-C026-416E-BB99-40FCF4FA87F6https://stanford-linear-accelerator-center.365.altium.com/designs/F5AB04C2-2ADF-42DF-B87B-5C40051BA7FCBoard trackingGT Readout ASICsPC_261_101_42_C00

Previous boards

Altium missing components

The components listed in the expansion box below are currently missing from the SLAC Altium library located on OneDrive (Altium_Yee_lib).

Expand
  • Components marked with (green star) are available from the Altium Manufacturer Part Search catalog with symbol and footprint
  • Components marked with (red star) have been created in a temporary library (schematic symbol only) which should be integrated into the OneDrive library at some point
  • Components marked with (blue star) have been requested
    • Components with strikethrough have been created after request

DC/DC

Connectors:

FPGA:

  • (XCKU15P-2FFVA1156E used earlier in PC_261_101_25_C00)
    • XCKU15P-2FFVA1760E (red star) (blue star)

    Altium 365 project folder:

    https://stanford-linear-accelerator-center.365.altium.com/designs/folder-077F97F3-88BC-43E1-A2A7-66F200D82CFA


    Digital Board

    GT-Readout-Platform-digital

    Analog Board

    GT-Readout-Platform-analog

    Carrier Template Board

    GT-Readout-Platform-carrier-template

    3D view

    Image Added

    Image Added

    Image Added

    Description

    Digital board for the GT Readout Platform with FPGA and optical transceivers

    Analog board for the GT Readout Platform with power supplies, monitoring and calibration circuit for the ASIC carrier board that plugs into it

    Template board for ASICs that plugs into the analog board in the GT Readout Platform

    Altium 365 project
    Board tracking

    ePixUHR100k 2x2 implementation


    		Multi-board projectCarrier Board
    3D view

    Image Added

    Image Added

    DescriptionA configuration of the GT Readout Platform with a 2x2 carrier of ePixUHR100k ASICs.Carrier board for a 2x2 configuration of ePixUHR100k ASICs for use with the GT Readout Platform
    Altium 365 project
    Board tracking

    ePixUHR100k 1x4 implementation


    		Multi-board projectCarrier Board
    3D view

    Image Added

    Image Added

    DescriptionA configuration of the GT Readout Platform with a 1x4 and 4x1 carrier of ePixUHR100k ASICs.Carrier board for a 1x4 configuration of ePixUHR100k ASICs for use with the GT Readout Platform
    Altium 365 project
    Board tracking

    SparkPix-S 1x4 implementation

    See HE project - SparkPix-S 1x4

    Previous boards


    partrequestsmanagement/Tasks/Details/DC73FD60-CF53-4AE5-889A-45753213E927

    Thermistor, humidity:

    • NHQM103B375T10(blue star)
    • HIH-5031-001 (green star) (blue star)

    Analog:

    ID:

    • DS2411R+T&R (green star) (blue star)

    Memory:

    Oscillator/clock:

    Other

    Gigabit transceiver:

    Passives:

    • Capacitors
      • 330uF, 4V, tantalum, AVX F950G337KBAAQ2
      • 0603, 4.7uF, 50V
      • 0402, 33pF, 50V, GCM1555C1H330JA16J
      • 0201, 68pF (CGA1A2C0G1E680J030BA) (green star) (blue star)
    • Resistors
      • 0402, 8k06 (CRCW04028K06FKED)(blue star)
      • 0402, 13k7 (CRCW040213K7FKED)(blue star)
      • 0402, 15k4 (CRCW040215K4FKED)(blue star)
      • 0402, 26k1 (CRCW040226K1FKED)(blue star)
      • 0402, 38k3 (CRCW040238K3FKED)(blue star)
      • 0402, 53k6 (CRCW040253K6FKED)(blue star)
      • RES, 0.001 OHM 1% 4 TERMINAL, 2512, Vishay Y14870R00100D9R (red star) (blue star)
      • 0402, 57k6 (CRCW040257K6FKED)(blue star)
      • 0402, 42k2 (CRCW040242K2FKED)(blue star)
      • 0402, 365R (CRCW0402365RFKED)(blue star)
      • 0 Ohms Jumper Chip Resistor 1206 (3216 Metric) Metal Element (Keystone Electronics 5108) (green star) (blue star)
      • 49R9, 1%, 1206, 1W, SUSUMU - HRG3216P-49R9-D-T1(blue star)
      • 0201, 130R (CRCW0201130RFKED)(blue star)
    • Inductors
      • XGL6030-122MEC (green star) (blue star)
      • Ferrite (Fair-Rite 2512065007Y6)(blue star)

    Block diagrams

    Digital board

    The digital board contains the FPGA, supporting ICs and the Amphenol optical transceiver module. The DC/DC on this board are the ones related to the components located here.

    Gliffy Diagram
    displayNamedigital-board-block-diagram
    namedigital-board-block-diagram
    pagePin33

    FPGA design resources

    Analog board

    The analog board contains all the DC/DC converters that are needed to support the different power rails of the ASICs (see above). The data and control signals between the ASICs and the FPGA are routed through this board between the two high-density connectors.

    Gliffy Diagram
    displayNameanalog-board-block-diagram
    nameanalog-board-block-diagram
    pagePin30

    Carrier board

    The carrier board contains the specific ASICs and any passive components that are needed.

    Gliffy Diagram
    displayNamecarrier-board-block-diagram
    namecarrier-board-block-diagram
    pagePin9


    Simulations

    GT to the ASICs

    TODO

    GT to the transceivers

    TODO

    Power distribution

    Using the "Power Analyzer by Keysight" plugin in Altium.

    Simulation of sinking power regulator at 0.6V output potential

    Presentations by Pietro

    View file
    name220824 - SparkPixS - Sinking current LDO.pdf
    height250
    View file
    name220830 - SparkPixS - Sinking current LDO - Update.pdf
    height250
    View file
    name220928 - SparkPixS - LT3091 Noise Spectral Density.pdf
    height250

    Simulation by Pietro

    • Source files: LT3091 test.zip
    • A LT1965 LDO feeds a 2.5 V (Vin) voltage to two LT3091 in parallel
    • At the outputs of the LT3091 there is a 2.4 A current source with a 1.2 V voltage source (will be 1.3 V in final application) in series that emulate the ASIC front-end
    • The SET pins have a 50 uA reference current source in LT3091
      • Since there are two in this configuration the total current is 100 uA
      • This means that the voltage is V=I*R=100e-6*19e3 = 1.9 V
      • This voltage is relative to the "GND" pins which are at a 2.5 V potential
      • The potential at the output is therefore 2.5-1.9 = 0.6 V
      • Closest standard value resistor is 19.1k that results in V = 1.91 V → Output is at 0.59 V

    Updated simulation with LT3806 and ballast resistor compensation

    • The LT3086 feeds the two LT3091's with 2.5 V
    • The LT3086 is fed with a 5 V supply
    • The Imonn signal is tapped off at a voltage divider which compensates for the two 10mR ballast resistors at the outputs of the LT3091's
    • Simulation file: LT3091_sinking_with_LT3086_and_compensation.asc

    Jira tasks for the project

    To do

    Jira
    serverSLAC National Accelerator Laboratory
    columnIdssummary,assignee,status
    columnssummary,assignee,status
    maximumIssues5
    jqlQuerylabels = "GT-readout-platform" and status = "to do"
    serverId1b8dc293-975d-3f2d-b988-18fd9aec1546

    In progress

    Jira
    serverSLAC National Accelerator Laboratory
    columnIdssummary,assignee,status
    columnssummary,assignee,status
    maximumIssues20
    jqlQuerylabels = "GT-readout-platform" and status = "In progress"
    serverId1b8dc293-975d-3f2d-b988-18fd9aec1546

    Expand
    titleArchived questions
    •  Route +6V or +24V between analog and digital board?
      •  If +6V: All first-stage converters (LT8648S) must be on one the board with the input TFM connector
      •  +24V between boards
    •  For the 0.6V sink:
    •  On which board does the power connector (TFM) go and which type (TFM-112, TFM-115, etc)? (update Connectors section)
      •  TFM-113-02-L-DH was used on the ePixHR250M_2x2_Camera
      •   Analog board
    •  Use FPGA transceivers for clocking the ASICs?
      •  Yes 
      •  One per ASIC?
        •  Yes
        •  I think one per ASIC is the best solution. Is there any reason why we should go for a clock splitter?
          •  Probably no unless we run out of connector pins
    •  Does the digital board need the analog ground (AGND)? (see grounding)
      •  Will have it anyway since the TFM power connector is on the digital board
    •  What's the expected operating temperature range?
      •  -25C → +50C
    •  Are the ASIC digital supply (G_DS_X) and I/O supply (G_IO_X) shared among all four ASICs?
      •  Yes
    •  Can the DC/DC architecture be simplified? Some ICs not in stock, see DC/DC converters
      •  Replace LMZ31530 (30A) with TPSM5D1806 in parallel mode (12A) since Vcc_int is estimated at 7A?
        •  No, the 20A version should be available (LMZ31520)
    •  Provide space to measure both input (manual) and output (ADC) currents for all DC/DC?
    •  TPSM5D1806 does not work for 6V to 5.5V as a pre-LDO regulator!
      •  For 5.5V output, the minimum input voltage is 9.6V. See Table 7-3 in datasheet.
      •  Change first-stage converter to output 5.5V/5.0V instead of 6V?
        •  Second-stage LMZ31520 (Vout=0.85V) should be OK
        •  Second-stage TPSM5D1806 (Vout=1.8V and 0.9V) should be OK
        •  Changed first-stage converter to 5.0V on digital board now
    •  Remove DC/DC monitor on digital board
    •  Do we have the CML current consumption numbers?
      •  Gang is saying around 20mA (15mA + 30% LVT) per ASIC TX Transceiver (for all frequencies). ASIC RX consumption is negligible 
      •  Update power estimation table with these numbers
    •  Check 24V to 1.8V (LT8648S) if it works at 30A
    •  Replace LT1764 with LT3083 for simpler paralleling circuitry (see power graph)?
      •  No, using multiple LT3086 in parallel instead (up to 3x)
    •  Substitute HS DAC: from MAX5719A to AD5541A?
    •  Does the cooling system include a Peltier cell?
      •  The Peltier cells were removed after ePixHR10k5fps. We now adopt HFE cooling for low temperature liquid chillers or CO2 cooling systems