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The GT Readout Platform aims to provide a readout for use with new pixel detectors developed at SLAC (≥ 2023), which use high-speed (> 1 Gbit/s) gigabit transceivers for their data output. See for example the SparkPix-IO prototype. It consists of three main parts (shown in the block diagram below):
The sections below describe the platform in more detail. Use the table of contents below to quickly find a specific section you might be looking for or use one of the useful resources on the right for quick access. |
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Table of contents
Table of Contents maxLevel 2 exclude \b(?:Table of contents|Useful resources|Pages under this one)\b|\*
Useful resources
- Jira Kanban board for this project
- TID-ID Edge Computing Systems
- Presentations:
- GT Readout Platform - Concept Design (pdf)(pptx)(Sharepoint)
- LCLS-II/HE 500kPix Detector (Sharepoint)
- Board design tracking: GT Readout ASICs
Pages under this one
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ASIC level requirements summary
| Requirement | ePixUHR | SparkPix-S | SparkPix-ED  |
|---|---|---|---|
| Frame rate | 100 kfps | 1 Mfps | 1 Mfps |
| Power supplies | 2.5 V Analog | 2.5 V Analog | 1.3 V (AS/DS/IO) |
| Power for each supply | ePixUHR - 35 kHz | SparkPix-S: supply/ground and power consumption | t.b.d. |
| Number of GT IOs per ASIC | 8 (outputs) | 8 (outputs) 1 clock in | t.b.d |
| Expected I/O speed | 5.25 Gbit/s | 5.25 Gbit/s | 10 Gbit/s |
Total data bandwidth | 42 Gbit/s | 42 Gbit/s | 80 Gbit/s |
Target Cameras
There are three targeted cameras for this project:
- 2x2 ePix/SparkPix
- 1M ePix to later be used as building block for 16M camera
- 2M SparkPix
Block diagrams
2x2 ePix/SparkPix
- ePixHR/UHR 2x2 would be 140k pixels
- SparkPix S would be 500k pixels
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1M ePix
- ePixHR/UHR in a 6x6 configuration would be 1.1M pixels
- ePixHR/UHR in a 6x5 configuration would be 1M pixels
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2M SparkPix S
- SparkPix S in a 4 x 4 configuration would be 2M pixels
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Parameter overview
2x2 ePix/SparkPix | 1M ePix | 2M SparkPix S | |||
Parameter (estimated) | Small Camera | Small Camera | Super tile | Super tile | Quad Camera |
Pixels | 129,024 px | 516,096 px | 967,680 | 1,161,216 px | 2,064,384 px |
Rate | 35 kHz / 100 kHz | 1 MHz | 35 kHz / 100 kHz | 35 kHz / 100 kHz | 1 MHz |
Focal Plane Area | 4 cm x 4 cm | 4 cm x 4 cm | 12 cm x 10 cm | 12 cm x 12 cm | 8 cm x 8 cm |
Front side footprint (window) | 5 cm x 5 cm | 5 cm x 5 cm | 14 cm x 1 2cm | 14 cm x 14 cm | 10 cm x 10 cm |
Power (only ASIC) | 0.016 kW/??? | 0.021 kW | 0.130 kW/??? | 0.144 kW/??? | 0.084 kW |
Weight | 1.5 kg | 1.5 kg | 9 kg | 10 kg | 6 kg |
Data volume | 56 Gbit/s/ 160 Gbit/s | 160 Gbit/s | 420 Gbit/s / 1190 Gbit/s | 504 Gbit/s / 1440 Gbit/s | 640 Gbit/s |
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From ASIC to FPGA 168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame @35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbit/s @100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbit/s From FPGA to PC 168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame @32k - 1 ASIC (35kHz/100kHz): 14 Gbit/s / 40 Gbit/s @140k - 4 ASIC (35kHz/100kHz): 56 Gbit/s / 160 Gbit/s @1M - 30 ASIC (35kHz/100kHz): 420 Gbit/s / 1.19 Tbit/s @1.1M - 36 ASIC (35kHz/100kHz): 504 Gbit/s / 1.44 Tbit/s @4M - 144 ASIC (35kHz/100kHz): 2 Tbit/s/ 5.76 Tbit/s @16M - 576 ASIC (35kHz/100kHz): 8.1 Tbit/s / 23 Tbit/s |
ASIC Power Requirements
ASIC Power Requirement | Analog Section | Digital Section | I/O Section | 0.6V Sink | Analog TPS | |||||
|---|---|---|---|---|---|---|---|---|---|---|
ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | |
Voltage | 1.3 V | 1.3 V | 1.3 V | 1.3 V | 1.3 V | 1.3 V | N/A | 0.6 V | 2.5 V | 2.5 V |
Required current | 10A (= 2.5 A * 4 ASIC) | 13.4 A (= 3.35 A * 4 ASIC) | 1.872 A (= 0.468 A * 4 ASIC) | 2.0 A (= 0.5 A * 4 ASIC) TBD | 1.6 A (= 0.4 * 4 ASIC) [1RX, 8TX, 8serializer and 2cm clkspine : ~ 317mA] | N/A | -8 A | 0.4 A (=0.1 * 4 ASIC) | ||
System Requirement | +1.3 V @ +17.5 A (Adding +30% current for PVT variation) | +1.3 V @ +3 A (Adding +30% current for PVT variation) [waiting for the new digital design] | +1.3 V @ +2.5 A (Adding +30% current for PVT variation) | +0.6 V @ -11 A This current is not provided by the LDO. But it passes through it. (Adding +30% current for PVT variation) | +2.5 V @ +0.5 A (Adding +30% current for PVT variation) | |||||
FPGA
Expand the sections below to see additional information about the FPGA that was selected for this project.
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*Done considering 1% Occupancy instead of maxing out the transceivers
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ePixUHR 140k 2x2 Detector System
SparkPix S – 500k 2 x 2 ASIC Detector System
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FPGA KU15P (-A1760) Kintex U+ voltage rails
From Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
| Name | Voltage |
|---|---|
| VCCINT | 0.85 V |
| VCCINT_IO | 0.85 V |
| VCCBRAM | 0.85 V |
| VCCAUX | 1.8 V |
| VCCAUX_IO | 1.8 V |
| MGTVCCAUX_LN/LS/RN/RS | 1.8 V |
| VCCADC | 1.8 V |
| MGTAVCC_LN/LS/RN/RS | 0.9 V |
| MGTAVTT_LN/LS/RN/RS | 1.2 V |
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Power calculation SpreadSheet: UltraScalePlus_XPE_2023_140kpx.xlsm
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Power
A GUI from Linear Technologies (now Analog Devices) called LTPowerPlanner has been used to calculate all the required currents and voltages in the system. It also calculates the estimated losses and efficiency of the system.
| Power block diagram | LTPowerPlanner | ||||||||||
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Board power maps
The figures below give an approximation of where the power is consumed on the readout and ASIC carrier boards. The numbers are from the LTPowerPlanner block diagram above.
| Digital board power map | Analog board power map | ePixUHR100k carrier board power map | SparkPix-S carrier board power map |
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DrawIO source file: power-maps.drawio | |||
Power rail current draw
Using worst-case values below for conservative estimate of the currents needed for the different supplies
Digital board
| Power supply rail | Part | Quantity | Max current |
|---|---|---|---|
| P0V85 | FPGA VCCINT/VCCINT_IO | 1 | 7 A |
| Total: | 7 A | ||
| P1V8 | SN74AXC4T774RSVR | 3 | 3*26 uA = 78 uA |
| SI5345A-D-GM | 2 | 2*260 mA = 520 mA | |
| FPGA VCCAUX | 1 | ~500 mA | |
| FPGA VCCAUX_IO | 1 | ~100 mA | |
| FPGA MGTVCCAUX | 1 | ~300 mA | |
| FPGA VCCO 0 | 1 | < 100 mA | |
| FPGA XADC_VCC | 1 | ~10 mA | |
| FPGA VCCO 64/65/66/67/68/70/71/72/91 | 1 | < 100 mA | |
| MT25QU01GBBB8E12-0SIT | 1 | 55 mA | |
| Total: | < 1.7 A | ||
| P0V9 | FPGA MGTAVCC | 1 | 4 A |
| Total: | 4 A | ||
| P1V2 | FPGA MGTAVTT | 1 | 5.5 A |
| Total: | 5.5 A | ||
| P3V3 | SI5345A-D-GM | 1 | 130 mA |
| LMK61E2BAA-SIAT | 2 | 2*196 mA = 392 mA | |
| FPGA VCCO 93/94 | 1 | < 50 mA | |
| SN74AHC1G04DBVR | 3 | 3*4 = 12 mA | |
| SN74LVC3G34DCUR | 3 | ~3*1 = 3 mA | |
| LEAP transceiver | 1 | 2.4 A | |
| Total: | < 3 A | ||
| P2V5 | XLL726371.428571I | 1 | 44 mA |
| 536FB156M250DG | 1 | 98 mA | |
| AT24C64D-MAHM-T | 1 | 3 mA | |
| FPGA VCCO 90 | 1 | < 100 mA | |
| DS2411R | 2 | < 10 uA | |
| Total: | < 0.5 A | ||
| P1V3 | SN74AXC4T774RSVR | 3 | 3*26 uA = 78 uA |
| Total: | < 0.1 A | ||
Analog board
| Power supply rail | Part | Quantity | Max current (ePixUHR100k) | Max current (SparkPix-S) |
|---|---|---|---|---|
| P1V3_DVDD | ASIC digital supplies | 4 | 4*0.5*1.2/2 A = 1.2 A | 4*0.5*1.2/2 A = 1.2 A (preliminary) |
| Total: | < 1.5 A | < 1.5 A | ||
| P1V3_IOVDD | ASIC digital supplies | 4 | 4*0.5*1.2/2 A = 1.2 A | 4*0.5*1.2/2 A = 1.2 A (preliminary) |
| Total: | < 1.5 A | < 1.5 A | ||
| P3V3D | ADS1217IPFBT | 1 | 275 uA | |
| LT3045 for P0V8_DC_BIAS | 1 | < 0.1 A | ||
| Total: | < 0.2 A | |||
| P0V8_DC_BIAS | ASIC GT bias | 4 | < 0.1 A | |
| Total: | < 0.1 A | |||
| P1V8D | AD9249BBCZ | 1 | 124 mA | |
| AD5541ABRMZ | 3 | < 1 mA | ||
| Total: | < 0.2 A | |||
| P1V3_A1VDD | ASIC analog supply | 1 | 2.5*1.2 A = 3 A | 3.15*1.2 = 3.78 A (preliminary) |
| Total: | 3 A | 3.8 A | ||
| P1V3_A2VDD | ASIC analog supply | 1 | 2.5*1.2 A = 3 A | 3.15*1.2 = 3.78 A (preliminary) |
| Total: | 3 A | 3.8 A | ||
| P1V3_A3VDD | ASIC analog supply | 1 | 2.5*1.2 A = 3 A | 3.15*1.2 = 3.78 A (preliminary) |
| Total: | 3 A | 3.8 A | ||
| P1V3_A4VDD | ASIC analog supply | 1 | 2.5*1.2 A = 3 A | 3.15*1.2 = 3.78 A (preliminary) |
| Total: | 3 A | 3.8 A | ||
| P3V3A | ADS1217IPFBT | 1 | 1.325 mA | |
| HIH-5031-001 | 1 | 0.5 mA | ||
| ADR360BUJZ | 1 | < 1 mA | ||
| ADR361BUJZ | 1 | < 1 mA | ||
| OPA2626IDGKR | 4 | 4*2*3.1 mA ≈ 25 mA | ||
| AD5541ABRMZ | 2 | < 1 mA | ||
| MAX4781ETE | 4 | < 1 mA | ||
| Total: | < 0.1 A | |||
| P2V5A | ASIC analog monitors | 4 | < 0.1 A | |
| Total: | < 0.1 A | |||
| P1V8A | AD8607ARMZ | 1 | 50 uA | |
| AD9249BBCZ | 1 | 429 mA | ||
| Total: | < 0.5 A | |||
| P2V5A_SINK | LDOs for 0.6 V sink | 4 | < 0.5 A | |
| Total: | < 0.5 A | |||
Table of Contents
Useful resources
Jira issues in progress
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High priority tasks and questions
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The tasks and questions below should be looked at as soon as possible since they might be blocking |
- Check 24V to 1.8V (LT8648S) if it works at 30A
- Verify the power plane thickness for high-current rails (request by Doering, Dionisio)
- Does the cooling system include a Peltier cell?
- Change the ASIC connector position
Jira server SLAC National Accelerator Laboratory serverId 1b8dc293-975d-3f2d-b988-18fd9aec1546 key TIDIDECS-26 - Replace LT1764 with LT3083 for simpler paralleling circuitry (see power graph)?
- Substitute HS DAC: from MAX5719A to AD5541A ?
- ASIC team is still not able to quote us on the digital section power consumption.
- For now I would proceed as if the requirement was double w.r.t the old version
- Request components for Altium library (see Altium Missing Components section)
- See
Jira server SLAC National Accelerator Laboratory serverId 1b8dc293-975d-3f2d-b988-18fd9aec1546 key TIDIDECS-2
- See
| title | Archived questions |
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- Route +6V or +24V between analog and digital board?
- If +6V: All first-stage converters (LT8648S) must be on one the board with the input TFM connector
- +24V between boards
- For the 0.6V sink:
- Is it really +0.6V and sinking current that is needed?
- Has this been done before?
- Special LDO config needed? (see design note from Analog)
Precision Current Sources and Sinks Using Voltage References
- Pietro has simulated and tested this with evaluation board
- On which board does the power connector (TFM) go and which type (TFM-112, TFM-115, etc)? (update Connectors section)
- TFM-113-02-L-DH was used on the ePixHR250M_2x2_Camera
- Analog board
- Use FPGA transceivers for clocking the ASICs?
- Yes
- One per ASIC?
- Yes
- I think one per ASIC is the best solution. Is there any reason why we should go for a clock splitter?
- Probably no unless we run out of connector pins
- Does the digital board need the analog ground (AGND)? (see grounding)
- Will have it anyway since the TFM power connector is on the digital board
- What's the expected operating temperature range?
- -25C → +50C
- Are the ASIC digital supply (G_DS_X) and I/O supply (G_IO_X) shared among all four ASICs?
- Yes
- Can the DC/DC architecture be simplified? Some ICs not in stock, see DC/DC converters
- Replace LMZ31530 (30A) with TPSM5D1806 in parallel mode (12A) since Vcc_int is estimated at 7A?
- No, the 20A version should be available (LMZ31520)
- Replace LMZ31530 (30A) with TPSM5D1806 in parallel mode (12A) since Vcc_int is estimated at 7A?
- Provide space to measure both input (manual) and output (ADC) currents for all DC/DC?
- For optimization of DC/DC
- High-Current True Zero-Ohm Jumpers: https://www.digikey.com/en/product-highlight/k/keystone/high-current-true-zero-ohm-jumpers
- Yes!
- TPSM5D1806 does not work for 6V to 5.5V as a pre-LDO regulator!
- For 5.5V output, the minimum input voltage is 9.6V. See Table 7-3 in datasheet.
- Change first-stage converter to output 5.5V/5.0V instead of 6V?
- Second-stage LMZ31520 (Vout=0.85V) should be OK
- Second-stage TPSM5D1806 (Vout=1.8V and 0.9V) should be OK
- Changed first-stage converter to 5.0V on digital board now
- Remove DC/DC monitor on digital board
- Do we have the CML current consumption numbers?
- Gang is saying around 20mA (15mA + 30% LVT) per ASIC TX Transceiver (for all frequencies). ASIC RX consumption is negligible
- Update power estimation table with these numbers
ASIC level requirements summary
2.5V Analog
1.3V (AS/DS/IO)
2.5V Analog
1.3V (AS/DS/IO)
0.6V (Current sink!)
8 (outputs)
1 clock in
1 clock in
t.b.d
(The current agreement is to have 8 outputs)
Total data bandwidth
Target Cameras
There are three targeted cameras for this project:
- 2x2 ePix/SparkPix
- 1M ePix to later be used as building block for 16M camera
- 2M SparkPix
Block diagrams
2x2 ePix/SparkPix
- ePixHR/UHR 2x2 would be 140k pixels
- SparkPix S would be 500k pixels
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1M ePix
- ePixHR/UHR in a 6x6 configuration would be 1.1M pixels
- ePixHR/UHR in a 6x5 configuration would be 1M pixels
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2M SparkPix S
- SparkPix S in a 4 x 4 configuration would be 2M pixels
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Parameter overview
2x2 ePix/SparkPix
1M ePix
2M SparkPix S
Parameter (estimated)
Small Camera
ePixHR/UHR – 140k
2x2 ASIC
Small Camera
SparkPix S – 500k
2x2 ASIC
Super tile
ePixHR/UHR – 1M
6x5 ASIC
Super tile
ePixHR/UHR – 1.1M
6x6 ASIC
Quad Camera
SparkPix S – 2M
4x4 ASIC
Pixels
129,024 px
(168 *192*4)
540,672 px
(352*384*4)
967,680
(168 *192*30)
1,161,216 px
(168 *192*36)
2,162,688 px
(352*384*16)
Rate
35kHz / 100kHz
1MHz
35kHz / 100kHz
35kHz / 100kHz
1MHz
Focal Plane Area
4cm x 4cm
4cm x 4cm
12cm x 10cm
12cm x 12cm
8cm x 8cm
Front side footprint (window)
5cm x 5cm
5cm x 5cm
14cm x 12cm
14cm x 14cm
10cm x 10cm
Power (only ASIC)
0.016 kW/???
Weight
1.5kg
1.5kg
9Kg
10kg
6kg
Data volume
56 Gbps/ 160 Gbps
160 Gbps
420 Gbps/ 1190 Gbps
504 Gbps/ 1440 Gbps
640 Gbps
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From ASIC to FPGA 168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame @35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps @100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps From FPGA to PC 168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame @32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps @140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps @1M - 30 ASIC (35kHz/100kHz): 420 Gbps / 1.19 Tbps @1.1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps @4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps @16M - 576 ASIC (35kHz/100kHz): 8.1 Tbps / 23 Tbps |
ASIC Power Requirement
Analog Section
Digital Section
I/O Section
0.6V Sink
Analog TPS
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
Voltage
1.3 V
1.3V
1.3V
1.3V
1.3V
1.3V
??? Maybe
0.6 V
2.5 V
2.5V
Required current
10A
(= 2.5 A* 4 ASIC)
13.4 A
(= 3.35A * 4 ASIC)
- Old digital design:
1.2 A (= 0.3 A * 4 ASIC)
-New digital design
????
- Old digital design
2.0 A (= 0.5 A * 4 ASIC)
-New digital design
????
1.6 A
(= 0.4 * 4 ASIC)
[1RX, 8TX, 8serializer and 2cm clkspine : ~ 317mA]
??? (If existing lower or equal than SparkPixS)
-8 A
(= -2A * 4 ASIC)
0.4 A
(=0.1 * 4 ASIC)
System Requirement
+1.3 V @ +17.5 A
(Adding +30% current for PVT variation)
+1.3 V @ +3 A
(Adding +30% current for PVT variation)
[waiting for the new digital design]
+1.3 V @ +2.5 A
(Adding +30% current for PVT variation)
+0.6 V @ -11 A
!this current is not provided by the LDO. But it passes through it.
(Adding +30% current for PVT variation)
+2.5 V @ +0.5 A
(Adding +30% current for PVT variation)
FPGA Selection
ePixUHR 140k
2x2 Detector
Specs
ePixUHR 1.1M
6x6 Detector
Specs
ePixUHR 1M
6x5 Detector
Specs
SparkPix-S 500k
2x2 Detector
Specs
SparkPix-S 2M
4x4 Detector
Specs
KU15P (-A1760)
Kintex Ultrascale+
KU15P (-A1156)
Kintex Ultrascale+
FPGA USED IN ePixHR250M
KU15P (-E1517)
Kintex Ultrascale+
XCVU160 (-C2104)
Virtex Ultrascale
XCVU190 (-A2577)
Virtex Ultrascale
VU13P (-A2577)
Virtex Ultrascale+
General IO (HD, HP)
96 HD, 416 HP
48 HD, 486 HP
96 HD, 416 HP
52 HD, 364 HP
0 HD, 448 HP
0 HD, 448 HP
High Speed GTs (GTH/GTY)
- ASIC data:
32 = 8 lanes * 4 ASIC
- Spare outputs :
4
- PGP communication:
12 = 12* 160 Gbps/ 275Gbps
(1 Amphenol Transceiver)
Total:
48 High Speed GTs
- ASIC data:
288 = 8 lanes * 36 ASIC
- Spare outputs :
0
- PGP communication:
72 = 12* 1.44 Tbps/ 275Gbps
(6 Amphenol Transceivers)
Total:
360 High Speed GTs
- ASIC data:
240 = 8 lanes * 30 ASIC
- Spare outputs :
0
- PGP communication:
72 = 12 lanes * 1.19 Tbps/ 275Gbps
(6 Amphenol Transceivers)
Suggested 3 transceivers 1.4x compression in the detector
Total:
312 High Speed GTs
(If considering 5x2 Modules, 104 GTs each)
- ASIC data:
32 = 8 lanes * 4 ASIC
- Spare outputs :
4
- PGP communication:
12 = 12* 160 Gbps/ 275Gbps
(1 Amphenol Transceivers)
Total:
48 High Speed GTs
- ASIC data:
128 = 8 lanes * 16 ASIC
- Spare outputs :
0
- PGP communication:
24* = 12* 495 Gbps/ 275Gbps
(2 Amphenol Transceivers)
Total:
152 High Speed GTs
76
(44 GTH/32 GTY)
28
(20 GTH/8 GTY)
56
(32 GTH/24 GTY)
104
(52 GTH/52 GTY)
120
(60 GTH/60 GTY)
128
(0 GTH/128 GTY)
Total Block RAM
34.6 Mb
34.6 Mb
34.6 Mb
115.2 Mb
132.9 Mb
94.5 Mb
UltraRam, HBM
36 Mb, None
36 Mb, None
36 Mb, None
None, None
None, None
360 Mb, None
Transceiver Speed
(GTH, GTY)
> 10 Gbps
> 10 Gbps
> 10 Gbps
> 10 Gbps
> 10 Gbps
GTH 16.3 Gb/s
GTY 32.75 Gb/s
Transceivers
GTH 16.3 Gb/s
GTY 16.3 Gb/s
Transceivers
GTH 16.3 Gb/s
GTY 32.75 Gb/s
Transceivers
GTH 16.3 Gb/s
GTY 30.5 Gb/s
Transceivers
GTH 16.3 Gb/s
GTY 30.5 Gb/s
Transceivers
GTY 32.75 Gb/s
Transceivers
Size
The PCB width is (preferably) 65 mm (2.56’’)
42.5 x 42.5 mm
35 x 35 mm
40 x 40 mm
47.5x47.5 mm
52.5 x 52.5 mm
52.5 x 52.5 mm
Cost
6-10 k$
5-9 k$
6-10k$
40 k$
50-70 k$
60-110 k$
Comments
This is fine for the 2x2 Systems.
This is fine for the SparkPix-S 4x4
The number of GTs in this FPGA does not fit any of the cameras we are targetting
This is fine for the 2x2 Systems.
For the larger systems we need more than 3 FPGAs
This is fine for the 2x2 Systems.
This is fine for the 2x2 Systems (assuming we can fit the real estate).
This is fine for the 2x2 Systems.(assuming we can fit the real estate)
*Done considering 1% Occupancy instead of maxing out the transceivers
Summarizing Table
Requirements
Characteristics
KU15P (-A1156) Kintex U+
| title | FPGA Size Comparison |
|---|
| title | Proposed System solutions |
|---|
ePixUHR 140k 2x2 Detector System
SparkPix S – 500k 2 x 2 ASIC Detector System
| Expand | ||
|---|---|---|
| ||
|
FPGA KU15P (-A1760) Kintex U+ voltage rails
From Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
| title | KU15P power estimation |
|---|
Power calculation SpreadSheet: UltraScalePlus_XPE_2023_140kpx.xlsm
System level
We would like to match the ePixHRM board dimensions to reuse cooling
Side entrance detector
- Existing 75x175mmx58:
- max envelope would be (100x175x75mm)
2.56x1.95"
- Can we do it smaller?
- What is the minimum amount of components that need to leave in this board?
System Power Consumption Breakdown
Board
Domain
Portion
Final Voltages
LDOs
DC/DC
DC/DC
Analog
Analog
ASIC
G_AS_0
1.3V @4.4A
← +1.3V
LT1764 x2 (LDO)
Max 6A (= 3A x2)
← +1.8V (TBD)
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
← +6 V
LT8648S x2
42V, 15A Synchronous Step-Down Silent Switcher 2
Max Current = 15*2 = 30A
(Around 93% efficiency for 24 to 6V at max load)
← +24 V
The current drawn by the 0.6V current sink should not be counted twice since its sourced by the G_AS.
The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W.
If using 1.8V as the LDO input, we are burning also (1.8-1.3)V*4.4A*4 = 9W.
The power drawn by the TPS should be less than 2W.
So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W.
Considering the efficiency curves of the DC/DC converters:
34/85%/93% =
43W Total Analog Power
(if we did the same calculation for ePixUHR would be 32W)
G_AS_1
1.3V @4.4A
← +1.3V
LT1764 x2 (LDO)
Max 6A (= 3A x2)
← +1.8V (TBD)
G_AS_2
1.3V @4.4A
← +1.3V
LT1764 x2 (LDO)
Max 6A (= 3A x2)
← +1.8V (TBD)
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
← +6 V
G_AS_3
1.3V @4.4A
← +1.3V
LT1764 x2 (LDO)
Max 6A (= 3A x2)
← +1.8V (TBD)
G_VG_0
0.6V @ -2.75A
← +0.6V
LT3091 x2 (LDO)
Max 3.0A (= 1.5A x2)
← +2.5V
LT3086 (LDO)
Max 2.1A
← +3V
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(>90% efficiency for this loads)
← +6 V
G_VG_1
0.6V @ -2.75A
← +0.6V
LT3091 x2 (LDO)
Max 3.0A (= 1.5A x2)
G_VG_2
0.6V @ -2.75A
← +0.6V
LT3091 x2 (LDO)
Max 3.0A (= 1.5A x2)
← +6 V
G_VG_3
0.6V @ -2.75A
← +0.6V
LT3091 x2 (LDO)
Max 3.0A (= 1.5A x2)
G_AS_2V5
2.5V @ <0.5 A
← +2.5V
DAC/ADC/Misc.
VDD_3V3
+3.3V @ <1A?
3.3 W
← +3.3V?
LT3086 (LDO)
Max 2.1A
HS ADC: ~350mA
Slow ADC: few mA
DACs: ~250 mA
Total 0.7A
Worst case scenario starting from 5V,
3.5W/85%/93% =4.4W
VDD_2V5
+3.3V @ <1A?
3.3 W
← +3.3V?
LT3086 (LDO)
Max 2.1A
VDD_1V8
+1.8V @ <1A?
1.8 W
← +1.8V?
LT3086 (LDO)
Max 2.1A
Digital
ASIC
G_DS_0
1.3V @3A
← +1.3V
LT3086 x2 (LDO)
Max 4.2A (= 2.1A x2)
← +1.8V (TBD)
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
← +6 V
LT8648S x2
42V, 15A Synchronous Step-Down Silent Switcher 2
Max Current = 15*2 = 30A
(Around 93% efficiency for 24 to 6V at max load)
← +24 V
For the digital consumption of the ASIC we do not have precise numbers regarding the new logic.
Let's use the old numbers.
1.3V*3A = 4W
While for the I/O voltage we have an expected 1.3V*2.5A = 3.25 W.
LDO losses = 0.5*5.5 = 2.75 W
10W / 85% / 93% = 13W (ASIC Digital and I/O)
(if we did the same calculation for ePixUHR would be 9.5W)
G_DS_X
1.3V @???A (CML simulations?)
← +1.3V
LT3086 x2 (LDO)
Max 4.2A (= 2.1A x2)
← +1.8V (TBD)
G_IO_0
1.3V @???A(CML simulations?)
← +1.3V
LT3086 x2 (LDO)
Max 4.2A (= 2.1A x2)
← +1.8V (TBD)
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
← +6 V
G_IO_X
1.3V @???A(CML simulations?)
← +1.3V
LT3086 x2 (LDO)
Max 4.2A (= 2.1A x2)
← +1.8V (TBD)
Digital
FPGA
VCCINT
0.85V @7.05 A
6 W
← +0.85V
LMZ31520 DC/DC Buck converter
3V to 14.5V input
20A
(Around 90% efficiency)
Max 17 W_out, 19 W_in
← +5 V
Max ~60 W
LT8638S x2
| Expand | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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17.1W /85%/93% =21.5W (FPGA)
VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX
1.8V @0.7A
1.3 W
← +1.8V
TPSM5D1806 (DC/DC)
PMIC
4.5V to 15V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
Max 16 W_out, 19 W_in
MGTAVCC +MGTYAVCC
0.9V @3.7A
3.3 W
← +0.9V
VCC_1.2V + MGTAVTT + MGTYAVTT
1.2V @5.5A
6.6 W
← +1.2V
TPSM5D1806 (DC/DC)
PMIC
4.5V to 15V input
Parallel 12A output
(Between 80% and 90% efficiency)
Max 15 W_out, 19 W_in
| |||||||||||
Bank IO, clocks, buffers, etc.
VDD_3V3
+3.3V @ <1A
3.3 W
| |||||
VDD_2V5
+2.5V @ <1A
2.5 W
← +2.5V
LT3086 (LDO)
Max 2.1A
LEAP Transceiver
|
| |||||
Component
Product number
Quantity
Input Voltage
Output Voltage
Max Current
Comment
For digital board first stage power (same as used in Power & communication board (PC_261_101_26_C00)
Texas Instruments WEBENCH
https://webench.ti.com/power-designer/switching-regulator
LMZ31520 - digital board - 5.0V to 0.85V
TPSM5D1806 - digital board - 5.0V to 1.8V and 0.9V
TPSM5D1806 - digital board - 5.0V to 1.2V
| Gliffy Diagram | ||||||||
|---|---|---|---|---|---|---|---|---|
|
Paralleling of DC/DC and LDOs from data sheets
| Gliffy Diagram | ||||||||
|---|---|---|---|---|---|---|---|---|
|
| Expand | ||
|---|---|---|
| ||
OLD Graph:
|
General I/O
| title | General IOs for the 2x2(numbers based on ePixHR250M) |
|---|
ePixUHR Signals (single ASIC)
N# Pins
Power Digital Signals
N# Pins
Digital Core Signals
N# Pins
P&CB Signals
N# Pins
Waveform/ ASIC Ctrl
5
LDO enables
7
Env. Monitors
7
Misce
24
Clk
2 (0 if also clk_matrix is sent via GT)
DCDC Syncs
2
Bias DAC
4
Spare
6
Slow Ctrl (SACI/Sugoi)
4
HS DAC
4
Digital Monitor
2
HS ADC
6+24+8 =38
Miscellan
5
Jitter Cleaner
12
Total
13
Total
9
Total
70
Total
30
TOTAL = 13 * 4(n.Asics) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP
| Expand | ||
|---|---|---|
| ||
For single ended → check the electrical specification
|
Other components
Component
Product number
Board
Operation Voltage
Power consumption
N# I/O needed
Needs substitution?
Quad SPI Configuration Memory
MT25QU01GBBB8E12
Digital
1.8 V
Max 50 mA
4
No, we can use HR pins
EEPROM
???
Digital
???
???
???
JTAG
Digital
1.8/1.5/1.2 V
4
No, we can either use HR or go to 1.2V
Analog Monitor (SlowADC) ADC
ADS1217
Both (key at the analog board, optional at the digital board)
AVDD =3V, DVDD =1.8V
< 1 mA
7
Maybe. The datasheet guarantees operation for digital down to 2.7V, in HR250 was put at 1.8. Check if it is fine!
Analog Monitor MUX (x5)
MAX4734
may be needed depending on the number of channels we decide to monitor (all voltages and currents to the ASIC, humidity,...)
AVDD =3V
< 1 uA
None
They are controlled by the ADC
Humidity sensor
HIH_5031_001
Analog
3 V
None
No
Thermistor
NTC_NHQM103B375T10
None
No
Oscillators
•371 MHz XLL726371.428571I
•156 MHz 536FB156M250DG
•48 MHz CX3225SB48000D0FPJC1
Digital
2.5 V
Both 1.8 V and 2.5V solutions can be found depending on the voltage we want to use
Clock Fanout
SI53340-B-GM
Digital
2.5 / 1.8V
Now is 2.5, probably can be switch to 1.8, but since its AC-coupled should not matter. Check if we can remove the 2.5 LDO
Clock Jitter cleaner
SI5345_64QFN
Digital
VDD = 3.3V, DVDD =1.8V
12 + n. clks
Programmable Oscillator
LMK61E2
Digital
3.3 V
Used?
High Speed ADC
AD9249
Analog
1.8 V
Max 58mW/channel:
58*12 = 700mW
38
No
ADC_MON_VCM Buffer
AD8607_MSO8
Analog
1.8V
Bias DAC (HV Ring)
MAX5443 (DAC) +
MAX14611 (Level Shifter) +
REF192GS (Voltage reference)
Analog
3.0 V (VCCA)
4
Maybe? Will the sensors have an HV ring?
ASIC clk fanout
SI53340-B-GM
Probably not needed
HS DAC (Vcalib_p)
MAX5719A(DAC)+
MAX14611 (Level Shifter) +
OP213 (Buffer)
MAX6126A41+(Vref)
Analog
5V
Why was this chosen? Do we need the 5 V supply?
HS DAC (Vcalib_p)
AD5541A (DAC)
+OPA2626(Buffer)
+ADR360B(Vref)
VDD = 3/3.3V
VLogic = 1.8V
Vref = 2V
Level Shifter for Power controllers
MAX3378EETD (x2)
MAX3373E_SOT23_8 (x1)
to be defined
1.8V -> 3.3V
Serial number
DS2411R
Carrier, analog and digital boards
Digital: 3.3V
Analog: 3.3V?
Carrier: 2.5V?
Line Equalizer
(check the one used for cryo)
Analog
Transceiver
- Ideal is to reuse the 300Gbps Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode power supply.
Board material
- Needs to be FR408HR or better
System level simulation
- GT to the ASICs
- GT to the transceivers
- Power drops
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DC/DC converters
Product number | Type | Input Voltage | Output Voltage | Max Current | Comment |
| LT8638S | Buck | 2.8V to 42V | 0.6V to 42V | 10A | DC/DC Step Down converter. Parallel operation possible. (same as used in Power & communication board (PC_261_101_26_C00) |
| TPSM5D1806 | Buck | 4.5V to 15V | 0.5V to 5.5V | Dual 6A / Single 12A | DC/DC PMIC |
| LMZ31520 | Buck | 3V to 14.5V | 0.6V to 3.6V | 20A | DC/DC Buck converter. 30A version LMZ31530. |
| LT3086 | LDO | 1.4V to 40V | 0.4V to 32V | 2.1A | Low Output Noise: 40µVRMS (10Hz to 100kHz). Parallel operation possible. |
| LT3091 | LDO | –1.5V to –36V | 0V to –32V | -1.5A | Negative Linear Regulator. Low Output Noise: 18µVRMS (10Hz to 100kHz). Parallel operation possible. |
Texas Instruments WEBENCH
https://webench.ti.com/power-designer/switching-regulator
LMZ31520 - digital board - 5.0 V to 0.85 V
TPSM5D1806 - digital board - 5.0 V to 1.8 V and 0.9 V
TPSM5D1806 - digital board - 5.0 V to 1.2 V
Optional bypass of LDOs for ASIC
There are optional bypass jumpers on the analog board, as shown in the diagram above, for providing power to the ASIC directly from the LT8638S switching regulators. This will bypass the LDOs and can be used to test the performance of the ASIC when it's powered from a "dirtier" power source.
| Warning | ||
|---|---|---|
| ||
Make sure to adjust the output voltage of the switching regulators from 1.8 V to 1.3 V before powering up with an ASIC as the 1.8 V can cause permanent damage! The LDOs that are bypassed should also be removed from the board. |
Paralleling of DC/DC and LDOs from data sheets
| Gliffy Diagram | ||||||||
|---|---|---|---|---|---|---|---|---|
|
| Expand | ||
|---|---|---|
| ||
OLD Graph:
|
System level
| Requirement | Parameters | Notes |
|---|---|---|
| Power supply | 24 V consistent with the HR detector | |
| Mechanical size | We would like to match the ePixHRM board dimensions to reuse cooling Side entrance detector
|
|
| Digital board | 2.56 x 5.265" | |
| Power and communication | 2.56 x 5.240" | |
| Carrier | 2.56 x 1.95" |
|
General I/O
| Expand | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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TOTAL = 13 * 4( n.Asics ) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP |
| Expand | ||
|---|---|---|
| ||
For single ended → check the electrical specification
|
Other components
| Expand | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Transceiver
- Ideal is to reuse the 300 Gbit/s Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode fiber optics.
- Amphenol Transceivers Product Presentation
- About the stock (at 12 December 2023):
- interconnect that is soldered on the board we have in stock :
- 10140369-201LF (qty.25)
- 10140369-101LF (qty.4)
- (I checked the parts and both of them say -101LF on the component. 201 is different only on the numbering on the label. So in total we have 29)
- Laser transceiver part:
- 10124588-410 (no heatsink) (qty.5)
- 10124588-411 (low profile heatsink)(qty.15)
- (Online you cannot find description of -410 and -411. I am pretty sure they are equivalent to the -310 and -311)
| Anchor | ||||
|---|---|---|---|---|
|
| Functionality | Observations | link |
|---|---|---|
| Carrier to analog board |
| https://docs.google.com/spreadsheets/d/1b_nFUIKPOlVZJwAgv-RxHJQhuoHP3wuV?rtpof=true&usp=drive_fs |
| Analog to digital board |
|
|
| External power supply |
| |
| Optical transceiver |
|
| Gliffy Diagram | ||||||||
|---|---|---|---|---|---|---|---|---|
|
| Expand | ||
|---|---|---|
| ||
|
Cooling block
See
| Jira | ||||||
|---|---|---|---|---|---|---|
|
| Current cooling block | Updated cooling block |
|---|---|
The photo below shows the current cooling block designs (straight and angled), which is for a 30x6 SEAM/SEAF connector between analog and digital board. | The screenshot below shows that a 40x8 SEAM/SEAF connector can fit by extending the cutout in the cooling block without interfering with the pipe. Orange lines are the outline of the cooling block and the pipes in it. The new connector is 10*1.27 = 12.7 mm longer. |
|
Team center DSG-000074563* DSG-000074553 |
| Anchor | ||||
|---|---|---|---|---|
|
- Separate ground come into the system through the TFM power connector on the digital board
- The HV supply ground and the Analog supply ground are connected to the same analog ground net
- The digital supply is connected to the digital ground net
- The analog and digital grounds are connected together on the digital board near the TFM power connector
| Gliffy Diagram | ||||||||
|---|---|---|---|---|---|---|---|---|
|
Clocks
There are four main clock sources:
- Oscillator for GTY transceivers for LCLS-II timing
- Oscillator for GTY transceivers for PGP communication
- Jitter attenuator with various input choices for FPGA logic and GTY transceivers
- Jitter attenuator with various input choices for FPGA logic and GTH transceivers
The SI53340 clock buffer only buffers the input clock source into four output clocks with low amount of jitter added. The SI5345B is a jitter attenuator and an "any-frequency" multiplier where one input is selected that is fed to a PLL which then feeds multipliers for the individual outputs. Each output can therefore be programmed to different frequencies, which are synchronous with the selected input clock.
Clock structure diagram
| Gliffy Diagram | ||||||||
|---|---|---|---|---|---|---|---|---|
|
ASIC GT clock generation
The gigabit transceivers (GTs) in the ASIC require a high-frequency clock (2-3 GHz) with low jitter. There is no PLL inside the ASIC so it has to be provided from an external source (see SparkPix-IOs: fast I/Os prototype (~5 Gb/s) on TSMC 130nm). The proposed architecture will use the GTH transceiver outputs of the Kintex UltraScale+ to generate a "clock" from a static "101010..." bit pattern.
| Gliffy Diagram | ||||||
|---|---|---|---|---|---|---|
|
ASIC GT AC-coupling
There are high-speed signals in both directions between the ASICs and the FPGA:
- Clock signals from the FPGA GTH TX to the ASIC GT CLK
- Data signals from the ASIC GT TX to the FPGA GTH RX
These could either be DC-coupled or AC-coupled, which means that a series capacitor in the order of ~100nF is placed in series with the signal somewhere along the path. It is also called DC-blocking capacitors as described by Dr. Howard Johnson in an article on his website. The question is, where to place the capacitors? Close to the transmitter, in the middle, close to the receiver or somewhere else? In Johnson's article he argues that the main effect of these capacitors will be an impedance mismatch because the package of the capacitor will be bigger than the trace itself and we end up with an impedance that is less than the nominal impedance Z0 of the transmission line. This will result in negative reflections. He then argues that the effect of such a reflection has to be considered in relationship to the symbol baud interval and if it's much less than 1/2 of the baud interval it will have a minimal effect. We are working with up to 6 Gbit/s which gives a baud interval of 167ps. With a propagation delay of around 150 ps/inch (source) it means that to have minimal impact it has to be much less than 1/4 inch (~6 mm), somewhere in the order 1/20 of an inch (~1.2 mm) which is not practical on a PCB with IC packages, passives and routing.
For these high-speed cases it is therefore not the distance of the capacitor from the transmitter that matters, but instead the layout and routing of the traces around the capacitor.The goal is instead to minimize the effect of the capacitor on the impedance of the trace. One example Johnson gives is to reduce the parasitic capacitance underneath the body of the capacitor with a keep-out region in the reference plane underneath. A similar concept is shown in a layout design guide (local pdf copy, see page 30) for an Intel Stratix 10 device.
If we look at the LEAP transceiver that we are using in this project we can see that it has the AC-coupling capacitors on both RX and TX inside the package itself. This probably ensures that the effect of the capacitors is reduced as much as possible and they might use very small package sizes.
In our case it's probably a question of physical constraints that define where we can place the capacitors. For all four ASICs we would need 4*8*2+4*2=72 capacitors for data and clocks. Placing these on the carrier board might be tricky. Having them on the analog board would be a tight fit due to all the power supplies it has. That leaves the digital board which should hopefully have enough space to make a "clean" implementation of these capacitors.
ASIC timing and control signals - voltage level translation
The ASIC timing (SRO, R0, ACQ and INJ) and control (GR_N, SACI_SEL[3..0], SACI_CLK, SACI_CMD and SACI_RSP) are 1.3 V CMOS signals in the ASIC that has be be interfaced with the FPGA banks. In previous systems (e.g. ePixHR10k 2M digital board (TXI)) these were 2.5 V CMOS and were driven directly from HD banks in the Kintex UltraScale+ (except for SACI_SEL and SACI_RSP that were driven via MAX3002 from 1.8 V HP banks).
In short, there are two types of voltage level translators: auto-sensing bidirectional ones with transmission gates that will pull up or down when a rising or falling edge are detected; directional ones which has input receivers in one voltage domain and output drivers in the other voltage domain. The auto-sensing ones seem to lack information about the timing characteristics in the datasheet which is probably because it depends on how it is used and the device that is driving the pins of the translator. The directional ones are probably a better fit for this application where we know the direction and want as high drive strength as possible to propagate from the digital board all the way to the ASIC on the carrier board.
| FPGA HD banks | FPGA HP banks | MAX3002 | MAX3378E | TI AXC series | TI TXU series | TI TXV series |
|---|---|---|---|---|---|---|
From DS922 datasheet:
| From DS922 datasheet:
| This was used on the previous TXI digital board.
| This was originally used in this design before the schematic review.
|
|
|
|
Resources
- TI Voltage Translation Buying Guide
- TI Supporting Time and Skew Sensitive Interfaces with TI's TXV Level-Shifter Portfolio
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Altium 365 project folder: https://stanford-linear-accelerator-center.365.altium.com/designs/folder-077F97F3-88BC-43E1-A2A7-66F200D82CFA
Digital Board GT-Readout-Platform-digital | Analog Board GT-Readout-Platform-analog | Carrier Template Board GT-Readout-Platform-carrier-template | |
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| Description | Digital board for the GT Readout Platform with FPGA and optical transceivers | Analog board for the GT Readout Platform with power supplies, monitoring and calibration circuit for the ASIC carrier board that plugs into it | Template board for ASICs that plugs into the analog board in the GT Readout Platform |
| Altium 365 project | |||
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ePixUHR100k 2x2 implementation
| Multi-board project | Carrier Board | |
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| 3D view |
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| Description | A configuration of the GT Readout Platform with a 2x2 carrier of ePixUHR100k ASICs. | Carrier board for a 2x2 configuration of ePixUHR100k ASICs for use with the GT Readout Platform |
| Altium 365 project | ||
| Board tracking |
ePixUHR100k 1x4 implementation
| Multi-board project | Carrier Board | |
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| 3D view |
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| Description | A configuration of the GT Readout Platform with a 1x4 and 4x1 carrier of ePixUHR100k ASICs. | Carrier board for a 1x4 configuration of ePixUHR100k ASICs for use with the GT Readout Platform |
| Altium 365 project | ||
| Board tracking |
SparkPix-S 1x4 implementation
See HE project - SparkPix-S 1x4
Previous boards
- Based mechanically on the boards from ePixHR250M_2x2_Camera_Documentation
- Also using some components as used in ePixHR10k Shingled Camera - 2.2MPix - with jaw movement
- Changes done to the system architecture compared to the boards in the camera above:
- The digital board with the FPGA will be moved to the bottom of the stack with the optical transceiver
- The analog board is at the top and interfaces between the carrier and the digital board
Block diagrams
Digital board
The digital board contains the FPGA, supporting ICs and the Amphenol optical transceiver module. The DC/DC on this board are the ones related to the components located here.
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FPGA design resources
- Kintex UltraScale+ Documentation
UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG575)
- Note: The PDF download has better resolution than the web version
- See page 322 - FFVA1760 (XCKU15P)
- XTP427 - UltraScale+ FPGA and Zynq UltraScale+ MPSoC and RFSoC Schematic Review Checklist (v1.14) (login required)
- UltraScale and UltraScale+ Package Device Pinout Files
Analog board
The analog board contains all the DC/DC converters that are needed to support the different power rails of the ASICs (see above). The data and control signals between the ASICs and the FPGA are routed through this board between the two high-density connectors.
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Carrier board
The carrier board contains the specific ASICs and any passive components that are needed.
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Simulations
- Digital board: PC_261_101_38_C00#Simulation
- Analog board: PC_261_101_39_C00#Simulation
- Carrier board: PC_261_101_41_C00#Simulation
Simulation of sinking power regulator at 0.6V output potential
Presentations by Pietro
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Simulation by Pietro
- Source files: LT3091 test.zip
- A LT1965 LDO feeds a 2.5 V (Vin) voltage to two LT3091 in parallel
- At the outputs of the LT3091 there is a 2.4 A current source with a 1.2 V voltage source (will be 1.3 V in final application) in series that emulate the ASIC front-end
- The SET pins have a 50 uA reference current source in LT3091
- Since there are two in this configuration the total current is 100 uA
- This means that the voltage is V=I*R=100e-6*19e3 = 1.9 V
- This voltage is relative to the "GND" pins which are at a 2.5 V potential
- The potential at the output is therefore 2.5-1.9 = 0.6 V
- Closest standard value resistor is 19.1k that results in V = 1.91 V → Output is at 0.59 V
Updated simulation with LT3806 and ballast resistor compensation
- The LT3086 feeds the two LT3091's with 2.5 V
- The LT3086 is fed with a 5 V supply
- The Imonn signal is tapped off at a voltage divider which compensates for the two 10mR ballast resistors at the outputs of the LT3091's
- Simulation file: LT3091_sinking_with_LT3086_and_compensation.asc
Jira tasks for the project
To do
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In progress
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- How are we going to prevent ePixHRM carriers to be connected in to the 100kfps digital board and vice-versa?
- Options could be mechanical pins or change connector polarities
- Or via serial ID (needs to have a database) via soft locks
- Routes all power, data and control signals to/from the ASICs
- Distributes the 24V from the power connector
- Routes data and control signals between the ASIC on the carrier and the FPGA on the digital board
- High Speed Characterization Report (17.5 mm stack height) [original PDF from Samtec]
- Optimal pin layout for differential in horizontal orientation of P and N pairs
- This is the same layout used by the FMC connector (FMC pinout table)
- Low-speed signals (HA, HB, LA) are rated at 2 Gbit/s
- High-speed signals (DP) are rated at 10 Gbits/s
- Should be on the bottom board (digital) because a pigtail is connected to it that is attached to the outside shell
- If if was on the top board (analog) there's a risk of damaging the ASICs and their wirebonds on the carrier
- Same as for the power connector
- Place close to FPGA due to 25 Gbit/s signals
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- Separate ground come into the system through the TFM power connector on the digital board
- The HV supply ground and the Analog supply ground are connected to the same analog ground net
- The digital supply is connected to the digital ground net
- The analog and digital grounds are connected together on the digital board near the TFM power connector
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Other notes
- FPGA intercommunication
- Co-design with the data reduction pipeline
- DFX for streaming pre-processing and eventually microAI, reusable building blocks
Cooling block
The photo below shows the current cooling block designs (straight and angled), which is for a 30x6 SEAM/SEAF connector between analog and digital board.
The screenshot below shows that a 40x8 SEAM/SEAF connector can fit by extending the cutout in the cooling block without interfering with the pipe. Orange lines are the outline of the cooling block and the pipes in it.
The new connector is 10*1.27 = 12.7 mm longer.
- Using Altium Designer
- Multi-board project: https://stanford-linear-accelerator-center.365.altium.com/designs/5186839B-3CA3-4D54-8947-817E5400B729
- Digital board: https://stanford-linear-accelerator-center.365.altium.com/designs/15351422-ADCD-4239-875B-3D8D5E0BD347
- Analog board: https://stanford-linear-accelerator-center.365.altium.com/designs/40A8ABB0-467C-443B-B76D-D732550EB38A
- Carrier template board: https://stanford-linear-accelerator-center.365.altium.com/designs/AE5F4BFE-DBC6-4B3C-9281-8A1FBAC9D0BA
- Based mechanically on the boards from ePixHR250M_2x2_Camera_Documentation
- Also using some components as used in ePixHR10k Shingled Camera - 2.2MPix - with jaw movement
- Changes done to the system architecture compared to the boards in the camera above:
- The digital board with the FPGA will be moved to the bottom of the stack with the optical transceiver
- The analog board is at the top and interfaces between the carrier and the digital board
- Naming:
- GT-Readout-Platform-single-carrier
- GT-Readout-Platform-single-digital
- GT-Readout-Platform-single-analog
The components listed in the expansion box below are currently missing from the SLAC Altium library located on OneDrive (Altium_Yee_lib).
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DC/DC
Connectors:
FPGA:
Thermistor, humidity:
Analog:
ID:
Memory:
Oscillator/clock:
Level-shifters:
Gigabit transceiver:
Passives:
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Block diagrams
Digital board
The digital board contains the FPGA, supporting ICs and the Amphenol optical transceiver module. The DC/DC on this board are the ones related to the components located here.
| Gliffy Diagram | ||||||
|---|---|---|---|---|---|---|
|
FPGA design resources
- Kintex UltraScale+ Documentation
UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG575)
- Note: The PDF download has better resolution than the web version
- See page 322 - FFVA1760 (XCKU15P)
- XTP427 - UltraScale+ FPGA and Zynq UltraScale+ MPSoC and RFSoC Schematic Review Checklist (v1.14) (login required)
- UltraScale and UltraScale+ Package Device Pinout Files
Analog board
The analog board contains all the DC/DC converters that are needed to support the different power rails of the ASICs (see above). The data and control signals between the ASICs and the FPGA are routed through this board between the two high-density connectors.
| Gliffy Diagram | ||||||
|---|---|---|---|---|---|---|
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Carrier board
The carrier board contains the specific ASICs and any passive components that are needed.
| Gliffy Diagram | ||||||
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Overview
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