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Category

Name

Direction

Clock domain

Width

Description

Clock & reset logic

axiClk

Input

-

1

AXI Lite clock

axiRst

Input

axiClk

1

AXI Lite reset

devClk_i

Input

-

1

Development clock

devRst_i

Input

Synced to devClk_i in DaqMux (for some reason)

1

Development logic reset

wfClk_i

Input

-

1

Ouput lanes' clock

wfRst_i

Input

wfClk_i

1

Output lanes' reset

DaqMux control signals and timing information

trigHw_i

Input

Synced to devClk_i in DaqMux

1

Trigger signal to start the DaqMux streaming

0 indicates no trigger event
1 indicates a trigger event

trigCasc_i

Input

Synced to devClk_i in DaqMux

1

Cascaded trigger input. Can be used along with trigHw_i when enabled in the register file

0 indicates no trigger event
1 indicates a trigger event

trigCasc_o

Output

devClk_i

1

Output trigger signal connected to the SW Trigger Enable control register

0 indicates no trigger event
1 indicates a trigger event

armCasc_i

Input

Synced to devClk_i in DaqMux

1

Cascaded trigger Arm. Arms the trigger and prepares DaqMux for trigger arrival

0 indicates no arm
1 indicates armed

armCasc_o

Output

devClk_i

1

Output cascade signal connected to the Arm HW Trigger control register

0 indicates no arm
1 indicates armed

freezeHw_i

Input

Synced to devClk_i in DaqMux

1

Adds invalid flag to the streams that are forwarded, and they will be discarded in one of the posterior blocks in the pipeline

0 indicates valid (not freeze)
1 indicates invalid (freeze)

timeStamp_i

Input

Synced to devClk_i in DaqMux

64

Time stamp coming from the AMC carrier core

bsa_i

Input

Synced to devClk_i in DaqMux

128

BSA information coming from the AMC carrier core

dmod_i

Input

Synced to devClk_i in DaqMux

192

Dmod timing information coming from the AMC carrier core

AXI Lite register memory mapped interface for reading and writing to register file

axilReadMaster

Input

axiClk

1

AXI Lite record containing

Read Address channel

araddr : slv(31 downto 0);
arprot : slv(2 downto 0);
arvalid : sl;

Read data channel

rready : sl;

axilReadSlave

Output

axiClk

1

AXI Lite record containing

Read Address channel

arready : sl;

Read data channel

rdata : slv(31 downto 0);
rresp : slv(1 downto 0);
rvalid : sl;

axilWriteMaster

Input

axiClk

1

AXI Lite record containing

Write address channel

awaddr : slv(31 downto 0);
awprot : slv(2 downto 0);
awvalid : sl;

Write data channel

wdata : slv(31 downto 0);
wstrb : slv(3 downto 0);
wvalid : sl;

Write ack channel

bready : sl;

axilWriteSlave

Output

axiClk

1

AXI Lite record containing

Write address channel

awready : sl;

Write data channel

wready : sl;

Write ack channel

bresp : slv(1 downto 0);
bvalid : sl;

Input lane array - data valid based

sampleDataArr_i

Input

devClk_i

N_DATA_IN_G

Input data stream array of 32-bit words

sampleValidVec_i

Input

devClk_i

N_DATA_IN_G

Input valids with each valid corresponding to the respective stream in that cycle

linkReadyVec_i

Input

devClk_i

N_DATA_IN_G

Indicate that the stream source is ready. If is 0, the DaqMux sets the Stream Error control register to 1.

Output lane array

rxAxisMasterArr_o

Output

wfClk_i

N_DATA_OUT_G

AXI compliant output data stream array of 32-bit words. Nonetheless, the type of rxAxisMasterArr_o is defined as follows in the AxiStreamPkg.vhd file

tValid : sl;
tData : slv(511 downto 0);
tStrb : slv(63 downto 0);
tKeep : slv(63 downto 0);
tLast : sl;
tDest : slv(7 downto 0);
tId : slv(7 downto 0);
tUser : slv(63 downto 0);

rxAxisSlaveArr_i

Input

wfClk_i

N_DATA_OUT_G

AXI streams data ready signals

rxAxisCtrlArr_i

Input

Synced to devClk_i in DaqMux

N_DATA_OUT_G

AXI stream control signals as follows

pause : sl;
overflow : sl;
idle : sl;

If pause is 1, the DaqMux will not start and error is set. Represents status(DONE_C) signal in the AxiStreamDmaRingWrite module of the waveforEngine. Not clear what is the meaning of this flag. Found this comment in that module

Code Block
-- status(DONE_C) indicates a push, but maybe more than one

...

Register name	Address	Access	Bits	Alias	Description
Control	0x0	RW	0	SW Trigger Enable	Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again.
			1	Cascade Trigger enable	Enabling/disabling cascaded trigger '0' - Disable Cascaded Trigger '1' - Enable Cascaded Trigger
			2	Auto Rearm HW Trigger	Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger '0' - Disabled (has to be armed with bit3 otherwise disabled) '1' - Enabled
			3	Arm HW Trigger	Arms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register.
			4	Trigger Clear Status	Trigger status will be cleared (On the rising edge).
			5	Daq Mode	Select the data acquisition mode ( Stream stops if Error occurs ) '0' - Trigger mode - Normal DAQ mode Has to be triggered to start every time '1' - Continuous mode - The data is framed and continuously streamed out after enabled. (Still requires a trigger to start) Disable the stream to stop
			6	Packet Header Enable	Add 128-bit header (otherwise only data will be inserted)(Applies only to Triggered mode only) '0' - Disabled '1' - Enabled
			7	SW Freeze Buffer	Freezes all enabled circular buffers
			8	HW Freeze Buffer Enable	Enabling/disabling hardware freeze buffer request '0' - Disabled '1' - Enabled
Status	0x1	RO	0	Software Trigger Status	Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ).
			1	Cascade Trigger Status	Cascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
			2	HW Trigger Status	Hardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
			3	HW Trigger Armed Status	Hardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs )
			4	Combined Trigger Status	Combined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] )
			5	Freeze Buffers Status	Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] )
Decimation	0x2	RW	15:0	Decimation Rate Divisor	Sample rate divider (Decimator): Averaging Enabled: (powers of two) 1,2,4,8,16,etc (max 2^12) Averaging Disabled (32-bit): 1,2,3,4,etc (max 2^16-1).Averaging Disabled (16-bit): 1,2,4,6,8,etc (max 2^16-1).
DataSize	0x3	RW	31:0	Data Buffer Size	Number of 32-bit words to forward at each trigger (Ignored in continuous mode) (if enabled header will be included in the first 14 words of data). Minimum size is 14 (the size of the header).
TimeStamp	0x4	RO	31:0	Timestamp[31:0]	Timestamp [31:0] - secPastEpoch
TimeStamp	0x5	RO	31:0	Timestamp[63:32]	Timestamp [63:32] - nsec
BSA	0x6	RO	31:0	bsa(0)	edefAvgDn
	0x7		31:0	bsa(1)	edefMinor
	0x8		31:0	bsa(2)	edefMajor
	0x9		31:0	bsa(3)	edefInit
TrigCount	0xA	RO	31:0	Trigger Count	Counts valid data acquisition triggers
DbgInputValid	0xB	RO	31:0	Debug Input Valid	All DaqMux AXI input streams valid signals
DbgLinkReady	0xC	RO	31:0	Debug Link Ready	All DaqMux AXI input streams ready signals
InputMuxSel	0x10	RW	4:0	Input Mux Select[0]	0x1x: Stream x: Channel select Multiplexer 0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29) Test mode will output counter data
	0x11-0x1E		4:0	Input Mux Select[1]-[14]
	0x1F		4:0	Input Mux Select[15]
DaqStatus	0x20-0x2F (one register for each of the 16 (enabled) lanes)	RO	0	Stream Pause	(rxAxisCtrlArr_i port signal) Raw diagnostic stream control pause (Waveform engine bufferDone signal. When an AXI frame is completely written to DRAM, this bit is set)
			1	Stream Ready	Debug flag: Raw diagnostic stream control Ready (Waveform engine FIFO output stream ready signal)
			2	Stream Overflow	(rxAxisCtrlArr_i port signal) Raw diagnostic stream control Overflow (set to 0 in waveform engine)
			3	Stream Error	Debug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped)
			4	Data source ready	Debug signal: The data source is ready. If not, DaqMux sets error signal to 1
			5	Stream Enable	Debug signal: Output stream enabled
			31:6	Frame Count	Number of 4096 word frames sent
DataFormat	0x30-0x3F (one register for each of the 16 (enabled) lanes)	RW	4:0	Sign Bit Position	Indicating sign extension point (all bits after sign bit will be overwritten with sign)
			5	Data Width	Data width 32-bit or 16-bit '0' : 32-bits '1' : 16-bits
			6	Sign enable	Signed/unsigned '0' : Unsigned '1' : Signed
			7	Decimation Averaging Enable	Decimation Averaging '0' : Disable '1' : Enable

...

freezeHw_i
trigHw_i
DAC input signals
- Data - sampleDataArr_i[13:7] to sampleDataArr_i[13] : AppCore dacValues[6:0] to dacValues[7]their valids
- Valids - sampleValidVec_i[7] to sampleValidVec_i[1313:7]: AppCore dacValids[6:0] to dacValids[6]
Debug input signals:
- Data - sampleDataArr_i[17:14] to sampleDataArr: AppCore debugValues[3:0]
- Valid - sampleValidVec_i[17:14] : AppCore debugValuesdebugValids[3:0] to debugValues[3]sampleValidVec_i[14] to sampleValidVec_i[17] : AppCore debugValids[0] to debugValids[6
LinkReady signals: Mapped to valids of all stream except for debug
- LinkReady[17:14]: 4'hF
- LinkReady[13:7]: dacValids[6:0]
- LinkReady[6:0]: adcValids[6:0]

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