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Notes: 

• The birth ID of 20UPGR91101015 was 20UPGR92101015 (which should be used for DB search) and the module ID changed when shipped to CERN. 
• eFuse burning of Chip 1 0x15448 ID had a mistake that burnt 0x15408 instead. ChipNameCheck during configuration may complain.

• Use the 16x1 configuration in both software and firmware (you can check the firmware with ./bin/specComTest, and reflash the firmware if needed).

• The 1 DP readout adaptor had 10KOhm resistor pulldown for each data line leg. This is deemed unnecessary and may introduce more noise. So they were remove as of May/12/2023. 
• There is an inconsistency in the 1DP readout adaptor design files. The DP pin numbers printed on adaptor PCB next to the DP connector disagree with the schematics (see table below).    

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Can be solved by boosting the amplitude and preemphasis of the CMD CML driver. According to Timon, the default ones are sufficient for the SCC but not for the quad module because of the additional flex + adapter card. Timon's recommended quad settings are:

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From tests, 3 chips on this module work pretty consistently with these settings while the last one (0x15448) always has some issues (only tested digital scans so far). Following Alex's initial observations, further setup checks seems to indicate chip 4 (0x15448) prefers cmlBias0/1=500/0.  

An explanation on the connectivity:

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The ITkPixV1.1 Digital Quad is based on the V2.4 common Quad hybrid design with its schematics  indicating that only two GTX output of each chip are physically connected to the module ZIF. The quad module ZIF interface and further connectivity details of the to the V1.0 Quad Readout Adaptor with 1 DP connector serving 1 line per FE (schematics) via straight-through module Q/C data flex is captured in the "ITkPixV1-Quad" tab of the RD53A Ring Connectivity Stanford Drive GoogleSheet. The Quad Readout Adaptor further down selects the data GTX channels to only keep one data GTX per FE to form the 4 channels on the single DP connector:  

• There is was an inconsistency in adaptor V1.0 documentation between schematics and silkscreen labels (Alex's original note referred to the silkscreen labels). The DP pins listed in the table are for DP connector at the edge of the adaptor card When DAQ connects to adaptor, while it should be noted that at the other end of a DP-DP cable the data lanes which swap 0↔3which turned out to be a problem of schematic PDF copy for v1.0 which was fixed by Aleksandra on May/22/2023. Actual schematic and PCB prints were OK all along.   

Note: that these GTX and Chip maps are the same as what we expect from DataMergeOutMux. In the standard DP cable pin mapping, (1,3) is data0, (4,6) is data1, (7,9) is data2,  and (10,12) is data3. That's why in our config file, we have: chip1 rx2, chip2 rx1, chip3 rx0, chip4 rx3. This means that as long as we are using this adapter with the same config files, we should expect 1 data lane per chip while scanning, with no data merging.

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