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Q&A

  • What is the amplitude of the voltage pulse required to emulate beam-line?
    • Clue: Not sure, but output voltage capabilities of DAC might give a clue also need to make sure not over-driving till break down
    • How much charge do we expect tripping to happen at?
      • "medium -> low is 2400 keV/pixel so 6.6*10**5 electrons/pixel. High->low is probably 1/3 that, but we don't use AHL currently, so I'd focus on AML if possible." – Philp Hart
    • Beamline Pulse duration?
      • "The pulse is a delta function - 50 femtoseconds or less, typically.  The pair creation energy in Si is about 3.6 eV." – Philp Hart
  • What is typical bias voltage applied on Detector Bias line to reverse bias the substrate?
  • At this bias or some known bias voltage what is the expected substrate capacitance for a entire sensor (there are asic 4 in parallel)? 
    • "The detector capacitance per pixel should be around 150fF" – Bojan
    • An ASIC is ~2x2[cm^2] at 176x192 pixels
    • Total Number of pixels = 2x (176x192) x 2 = 352x384 = 135168 → 20.3nF
  • When the beam hits the substrate, which way does the current flow (in/out of pixel front-end) or (assuming substrate is negatively biased) that the current being drawn from the pixel front-end is less/more negative when a pulse hits (positive/negative voltage pulse)?
    • "It's for sure positive (not sure the actual voltage value). The baseline of the preamplifier is around 2V and it swings down when there is a signal."–Bojan 
  • What is the capacitance vs. bias curve of substrate?  
    • See testing section above