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To run the manual calibration procedure, you need to have detector at least configured once (Firmware/ASIC configuration). If you ran this previously, skip this step. If not, do the following step.You may want to always run this command to set these values to default.
Firmware/ASIC configuration: Open the Rogue interface, and In the InitASIC list, type [4,1,1,1,1] and hit enter. This will not configure the Silabs PLL, and use the default configuration with clock of 168Mhz and configure all ASICs with default.
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Important note: This function generates some files in the <scripts> folder (namely all_errorsX.csv, delay_spaceX.csv, run_resultsX.csv, and delay_spaceX.csv where X is 0 to 3). If these files already exist, the software will crash. So you need to delete these files, then run the script.
Once your settings are correct, hit the start button, and wait till Progress reaches 1.00 and Message says Done.
Upon a successful finish, this should generate an all_errorsX.csv file where X is 0-3 in the same folder where you ran the software (software/scripts). Navigate to that folder, and
Snapshot of values obtained automatically vs manual (Carrier 2, digital C00-01)
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and run the following script to see the error scan plots.
| Code Block |
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| language | bash |
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| theme | RDark |
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| title | Generate error scan plots |
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# run drawEyes.py script for ASIC3 and number of taps set to 64
(rogue_v6.1.3) dnajjar@rdsrv314 (addTriggerGen) $ python drawEyes.py 3 64 |
A window will open showing the error scans for ASIC 3 lanes
Image Added
How to interpret the error scan
The Y axes is error, and the X axis is the number of taps normalized to 1024 (10 bit delay register). If at any point the Y axes is 0, then you have a zero error point for that specific delay value (X).
Example: In the image above, Lanes 16, 22, and 23 seem dead.
AFter documenting, delete the file ((namely all_errorsX.csv, delay_spaceX.csv, run_resultsX.csv, and delay_spaceX.csv where X is 0 to 3)) using the following command:
>
| Code Block |
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rm *.csv (in the /scripts folder)
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When you are done with this function, run ">init ASIC" for clean up
| Expand |
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| title | SspMonGrp[0] (ASIC0) (automatic) |
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SspMonGrp[0]:
enable: True
LockedCnt[0]: 0x0
LockedCnt[1]: 0x4
LockedCnt[2]: 0x2
LockedCnt[3]: 0x2
LockedCnt[4]: 0x3
LockedCnt[5]: 0x4
LockedCnt[6]: 0x2
LockedCnt[7]: 0x2
LockedCnt[8]: 0x3
LockedCnt[9]: 0x4
LockedCnt[10]: 0x2
LockedCnt[11]: 0x3
LockedCnt[12]: 0x3
LockedCnt[13]: 0x3
LockedCnt[14]: 0x2
LockedCnt[15]: 0x2
LockedCnt[16]: 0x3
LockedCnt[17]: 0x4
LockedCnt[18]: 0x2
LockedCnt[19]: 0x3
LockedCnt[20]: 0x3
LockedCnt[21]: 0x4
LockedCnt[22]: 0x2
LockedCnt[23]: 0x3
BitSlipCnt[0]: 0x2c2d
BitSlipCnt[1]: 0x2c3f
BitSlipCnt[2]: 0x2c2a
BitSlipCnt[3]: 0x2c27
BitSlipCnt[4]: 0x2c31
BitSlipCnt[5]: 0x2c2d
BitSlipCnt[6]: 0x2c28
BitSlipCnt[7]: 0x2c2e
BitSlipCnt[8]: 0x2c27
BitSlipCnt[9]: 0x2c3b
BitSlipCnt[10]: 0x2c28
BitSlipCnt[11]: 0x2c2c
BitSlipCnt[12]: 0x2c39
BitSlipCnt[13]: 0x2c3c
BitSlipCnt[14]: 0x2c2c
BitSlipCnt[15]: 0x2c2a
BitSlipCnt[16]: 0x2c3b
BitSlipCnt[17]: 0x2c2b
BitSlipCnt[18]: 0x2c2a
BitSlipCnt[19]: 0x2c26
BitSlipCnt[20]: 0x2c17
BitSlipCnt[21]: 0x2c27
BitSlipCnt[22]: 0x2c2a
BitSlipCnt[23]: 0x2c2a
ErrorDetCnt[0]: 0xffff
ErrorDetCnt[1]: 0xffff
ErrorDetCnt[2]: 0xffff
ErrorDetCnt[3]: 0xffff
ErrorDetCnt[4]: 0xffff
ErrorDetCnt[5]: 0xffff
ErrorDetCnt[6]: 0xffff
ErrorDetCnt[7]: 0xffff
ErrorDetCnt[8]: 0xffff
ErrorDetCnt[9]: 0xffff
ErrorDetCnt[10]: 0xffff
ErrorDetCnt[11]: 0xffff
ErrorDetCnt[12]: 0xffff
ErrorDetCnt[13]: 0xffff
ErrorDetCnt[14]: 0xffff
ErrorDetCnt[15]: 0xffff
ErrorDetCnt[16]: 0xffff
ErrorDetCnt[17]: 0xffff
ErrorDetCnt[18]: 0xffff
ErrorDetCnt[19]: 0xffff
ErrorDetCnt[20]: 0xffff
ErrorDetCnt[21]: 0xffff
ErrorDetCnt[22]: 0xffff
ErrorDetCnt[23]: 0xffff
EyeWidth[0]: 0xff
EyeWidth[1]: 0xff
EyeWidth[2]: 0xff
EyeWidth[3]: 0xff
EyeWidth[4]: 0xff
EyeWidth[5]: 0xff
EyeWidth[6]: 0xff
EyeWidth[7]: 0xff
EyeWidth[8]: 0xff
EyeWidth[9]: 0xff
EyeWidth[10]: 0xff
EyeWidth[11]: 0xff
EyeWidth[12]: 0xff
EyeWidth[13]: 0xc0
EyeWidth[14]: 0xff
EyeWidth[15]: 0xff
EyeWidth[16]: 0xff
EyeWidth[17]: 0xff
EyeWidth[18]: 0xff
EyeWidth[19]: 0xff
EyeWidth[20]: 0xff
EyeWidth[21]: 0xff
EyeWidth[22]: 0xff
EyeWidth[23]: 0xff
Locked: 0xffffff
UsrDlyCfg[0]: 0xdb
UsrDlyCfg[1]: 0xdb
UsrDlyCfg[2]: 0xdb
UsrDlyCfg[3]: 0xdb
UsrDlyCfg[4]: 0xdb
UsrDlyCfg[5]: 0xdb
UsrDlyCfg[6]: 0xdb
UsrDlyCfg[7]: 0xdb
UsrDlyCfg[8]: 0xdb
UsrDlyCfg[9]: 0xdb
UsrDlyCfg[10]: 0xdb
UsrDlyCfg[11]: 0xdb
UsrDlyCfg[12]: 0xdb
UsrDlyCfg[13]: 0xdb
UsrDlyCfg[14]: 0xdb
UsrDlyCfg[15]: 0xdb
UsrDlyCfg[16]: 0xdb
UsrDlyCfg[17]: 0xdb
UsrDlyCfg[18]: 0xdb
UsrDlyCfg[19]: 0xdb
UsrDlyCfg[20]: 0xdb
UsrDlyCfg[21]: 0xdb
UsrDlyCfg[22]: 0xdb
UsrDlyCfg[23]: 0xdb
DlyConfig[0]: 0x7f
DlyConfig[1]: 0x17b
DlyConfig[2]: 0xfc
DlyConfig[3]: 0x7f
DlyConfig[4]: 0x7f
DlyConfig[5]: 0x178
DlyConfig[6]: 0x8c
DlyConfig[7]: 0x11c
DlyConfig[8]: 0x7f
DlyConfig[9]: 0x168
DlyConfig[10]: 0xe8
DlyConfig[11]: 0x14f
DlyConfig[12]: 0x7f
DlyConfig[13]: 0x63
DlyConfig[14]: 0x94
DlyConfig[15]: 0x117
DlyConfig[16]: 0x7f
DlyConfig[17]: 0xb9
DlyConfig[18]: 0x92
DlyConfig[19]: 0x111
DlyConfig[20]: 0x7f
DlyConfig[21]: 0x113
DlyConfig[22]: 0x7f
DlyConfig[23]: 0xc5
DATA_WIDTH_G: 16
NUM_LANE_G: 24
EnUsrDlyCfg: 0x0
MinEyeWidth: 0x50
LockingCntCfg: 0xffff
BypFirstBerDet: 0x1
Polarity: 0x0
GearboxSlaveBitOrder: 0x0
GearboxMasterBitOrder: 0x0
MaskOffCodeErr: 0x0
MaskOffDispErr: 0x0
MaskOffOutOfSync: 0x0
IdleCode: 0xffffff
LockOnIdleOnly: 0x0
RollOverEn: 0x0 |
...
