13JAN2017: Larry and Pietro: CHESS2 Configurations for different speeds

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Slow Clock	Fast Clock	CLK_bit_sel	clk_dly	rd_1	rlt_1	wrd_1	wrd_2	rd_2	rlt_2	Comment
20 MHz	160 MHz	0x0	0x0	0x0	0x2	0x7	0x7	0x0	0x2	All default values
31.25 MHz	250 MHz	0x0	0x0	0x0	0x2	0x7	0x7	0x0	0x2	All default values
40 MHz	320 MHz	0x0	0x0	0x0	0x2	0x3	0x3	0x0	0x2
45.45 MHz	363.6 MHz	0x0	0x0	0x0	0x2	0x3	0x3	0x0	0x2	50 MHz	400 MHz

31JAN2017: Larry: Std. Resistivity ASIC's PSUB voltage v.s. current draw

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