Several people provided input ot this diagram : Eric^3 (Siskind, Grove, Charles) and Martin Kocian.
If there are mistakes they are mine and please point me to a better timing diagram and I will gladly update this one since I am not an expert (Eduardo)
Important Detector Register Settings for end-to-end runs (baseline data taking)
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- TKR DAC (threshhold, range) (GTEM/GTCC/GTRC/GTFE/dac)) : (22 to 36, 0) for 1/3 of a MIP
ACD
- Note: if veto delay changes then change hitmap and hold delay by the same amount in the opposite direction so that the sum of veto_delay+ hitmap delay is constant and equal to 38 (with the current settings) and veto_delay + hold_delay is constant and equal to 40.
- Delay from ACD trigger discriminator to AEM trigger primitive formation (GAEM/GARC/veto_delay) : 0 16
- Stretch width of ACD trigger primitive (GAEM/GARC/veto_width): 5
- ADC acquisition time (GAEM/GARC/adc_tacq) : 0
- Delay from ACD trigger primitive to AEM hitmap data latch (GAEM/GARC/hitmap_delay): 6 22 (from Martin Kocian) and it does not add to the diagram at the bottom!
- Stretch width of ACD trigger primitive to AEMXS hitmap data latch (GAEM/GARC/hitmap_width) : 0 15 (for self-trigger or not from M. Kocian)
- Delay from trigger to hold (GAEM/GARC/hold_delay): 34 24
- Bias Dac (GAEM/GARC/GAFE/bias_dac): Set using AcdLeHeBiasCal script
- Zero suppresion threshold (GAEM/GARC/pha_threshold_xx): Set using AcdPedestal script
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