Page History

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The studies are split up into testing that can be performed using the development board and the full DAQ.

Tasks for new hybrid design

Tails and double peak structure in some pedestal distributions

Every 32nd ch/APV show double peak: reflection?

Noisy APV chips from test run: hybrid or apv?

Out of sync issue (often at start of run); what caused this

Bottom layer 3 in test run had issues; bad hybrid?

Edge channel noise (do we care)

35ns shaping time operation

Cold operation

Development Board Testing 2013

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• Leakage current and noise vs bias
• At nominal bias (80V)
• Noise, pedestal, gain,t0

Shaping time to 35ns

Establish operating points at this shaping time.

Tasks:

• Redo all calibration from QA: noise, pedestal, gain, t0, with Tp=35ns

Understand absolute scale

GUI indicates 18125e- being injected rather than 25000e- (nominal)

Tasks:

• Use source to calibrate this absolute scale

Double peak structure in pedestal distributions

Are these caused by reflections or pedestal shifting

Tasks:

Operational stability over time

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Full Test Run SVT  Testing 2013

 TBF

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Extract noise, pedestal, t0, gain

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Extract noise, pedestal, t0, gain with 35ns shaping time

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What caused the APV chips to go out of sync; usually happened at start of run

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Look at noisy chips in Top L5, Top L4 and Top L10

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Look at Bottom L3; higher currents than the others

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Study FIR setting; every 32nd channel had double peak