SVT DAQ QA Studies 2013

SVT DAQ QA Studies 2013

Goal: Improve our understanding of the SVT DAQ and in particular study issues identified during the QA and operation of the Test Run.

The studies are split up into testing that can be performed using the development board and the full DAQ.

Tasks for new hybrid design

Tails and double peak structure in some pedestal distributions

Every 32nd ch/APV show double peak: reflection?

Noisy APV chips from test run: hybrid or apv?

Out of sync issue (often at start of run); what caused this

Bottom layer 3 in test run had issues; bad hybrid?

Edge channel noise (do we care)

35ns shaping time operation

Cold operation

Development Board Testing 2013

Establish baseline performance

Redo QA tasks to establish baseline understanding of the development board equipment.

Tasks:

• Leakage current and noise vs bias
• At nominal bias (80V)
• Noise, pedestal, gain,t0

Shaping time to 35ns

Establish operating points at this shaping time.

Tasks:

• Redo all calibration from QA: noise, pedestal, gain, t0, with Tp=35ns

Understand absolute scale

GUI indicates 18125e- being injected rather than 25000e- (nominal)

Tasks:

• Use source to calibrate this absolute scale

Double peak structure in pedestal distributions

Are these caused by reflections or pedestal shifting

Tasks:

Operational stability over time

Run calibrations/pedestals for same chip/sensor over hours/days

Tasks:

Operation at cold temperature

Establish experience and understand APV25 behavior at lower temperatures. We'd like to understand and benchmark performance for a few different temperatures.

Temperature operating points (in C):

Tasks:

• Setup hardware needed for tests and identify halfmodule to be used
• Establish APV25 operational settings for all temperatures
• Study leakage current,power consumption, noise, gain, t0 resolution vs temperature

Edge channel noise on APV25

Tasks:

Run at clock frequency of about 50MHz

Tasks:

Full Test Run SVT  Testing 2013

Extract noise, pedestal, t0, gain

Extract noise, pedestal, t0, gain with 35ns shaping time

What caused the APV chips to go out of sync; usually happened at start of run

Look at noisy chips in Top L5, Top L4 and Top L10

Look at Bottom L3; higher currents than the others

Study FIR setting; every 32nd channel had double peak