Requirements
- SUGOI = SLAC Ultimate Gateway Operational Interface
- 凄い (or すごい or Sugoi) is a word that's typically used when you're left awestruck out of excitement or feel overwhelmed
Requirements
- Targeted for ASIC register communication and timing/trigger synchronization
- point-to-point or daisy chain communication
- Support up to 15 devices in a daisy chain
- Serial Encoding: 8B10B
- DC balanced
- Targeting FPGA/ASIC communication to over fiber optic or long copper cables
- Serial Rate: Same as reference clock sent to ASIC
- Supports fixed latency communication
- Register access:
- Only supports 32-bit aligned addresses and 32-bit word single (non-burst) transactions
Control Codes
The IDLE code is sent when no data frame and no trigger code is being sent. The GR is used to send a "global reset" to all the ASIC digital logic. Both IDLE and GR are "comma" codes such that the RX alignment gearbox can align to either of these codes (e.g. power up and start up the ASIC with only setting GR codes for a long period of time).
Trigger codes can be sent at any time, independent of the state of the data transport. There are 8 trigger codes that are mapped to a 8-bit trigger operation code bus. The GR is used to send a "global reset" to all the ASIC digital logic. The SOF code is used to indicate the start of a data payload transportWhen the trigger code is detected in the ASIC, a single cycle strobe will be generate on a bit of this 8-bit trigger bus.
The SOF/EOF codes are used for data framing. After the SOF either , the data payload (or trigger code) is sentis sent (non-control codes). After the last data payload byte, the EOF code is sent. During the data payload transport, any non-SOF or non-EOF control code is allow to be interleaved into the bit stream such that fixed trigger latency on the 8-bit trigger bus can be achieved.
IDLE | K28.5 (Comma)
|
SOF (Start of Frame) | K28.0 |
EOF (End of Frame) | K28K30.17 |
Trigger Code[BIT=0] | K28.2 |
Trigger Code[BIT=1] | K28.3 |
Trigger Code[BIT=2] | K28.4 |
Trigger Code[BIT=3] | K28.6 |
Trigger Code[BIT=4] | K28.7 (Comma) |
Trigger Code[BIT=5] | K23.7 |
Trigger Code[BIT=6] | K27.7 |
Trigger Code[BIT=7] | K29.7 |
GR (Global Reset) | K30.7K28.1 (Comma)
|
Data Frame Format for Register Access
The FPGA sends request messages to the ASIC in the serial protocol data payload tranport (in-between SOF and EOF). The ASIC processes the message and responds back to the FPGA. Only 1 message is in flight at any time to remove the requirement of back pressuring the link. Both the request message and responds message are the same size (11 bytes).
The daisy chaining of multiple ASIC is achieved via the header's device address field. When the ASIC received the header and the device field is 0x1, then the ASIC will process the register request message else pass it through. For each daisy chain stage and when device address is non-zero, the TX device address field is decremented by 1 from the RX device address. Example: You have two ASICs in the daisy chain. You would use device address = 0x1 to do register access on the first device and device address = 0x2 to do register access on the seconds device.
ASIC Inbound (FPGA Outbound) Request Format
Byte Offset | Name | Description | Note |
---|
0 |
Version Must be 0x1 | 1 | - Operation Type
- Device Address
| |
OpCode[7Operation Code | 0x0Non-Posted Read=Non-Posted Write0x2=Posted Write0x3=NULL0x4 ~ 0xFF (unused)- BIT[3]:
- BIT[7:4] = Device index on daisy chain
|
1 |
2 | TID[7:0] | Transaction ID | Used for debugging |
3 | DevAddr[7:0] | Device Address | - Used in daisy chain mode only
- 0xFF is a broadcast for all device
|
4 | RegAddr[31:24] | Register Address | |
5- RegAddr[1:0] must be zero for 32-bit address alignment
|
2 | RegAddr[23:16] |
6785 | WriteData[31:24] | Write Data | - Only used for write operations
|
91011 | 8 | WriteData[7:0] |
9 | Footer[7:0] | Responds Value | - footer bitwise OR'd for all daisy chain responds
|
10 | Checksum[7:0] | Checksum | - Calculated from all data payload bytes
- ByteOffset[9:0]
- One's complement
|
WriteData[7:0]ASIC Outbound (FPGA Inbound) Response Format
...
Byte Offset | Name | Description | Note |
---|
0 | VersionHeader[7:0] | | Echoed back |
1 | OpCode[7:0] | Operation Code | Echoed back |
2 | TID[7:0] | Transaction ID | Echoed back |
3 | DevAddr[7:0] | Device Address | Echoed back |
- Operation Type
- Device Address
| - Version number = Echoed back
- Operation Type = Echoed back
- Device Address:
- if 0x0 = Echoed back
- Else decremented by 1 from request's device address
|
14 | RegAddr[31:24] | Register Address | Echoed back |
52 | RegAddr[23:16] |
63 | RegAddr[15:8] |
74 | RegAddr[7:0] |
85 | MemData[31:24] | Memory Data | - Only used for non-posted operations
- Either read or write data depending on OP-code value
- Returns the read data if read operation
- Returns the write data if write operation
|
69 | MemData[23:16] |
107 | MemData[15:8] |
118 | MemData[7:0] |
129 | RespondFooter[7:0] | Responds Value from Transaction | Only used for non-posted operations. non-zero if error - BIT0 BIT[1:0] = Memory Transaction Responds
- BIT1 BIT2 = Version Mismatch Error
- BIT2 BIT3 = non 32-bit address alignmentBIT3
- BIT4 = Framing Errorchecksum error
- BIT[7:45] = 0x0
|
10 | Checksum[7:0] | Checksum | - Calculated from all data payload bytes
- ByteOffset[9:0]
- One's complement
|
References
- "SLAC Ultimate Gateway Operational Interface (SUGOI) Protocol for Fiber Optic ASIC/FPGA Communication": https://ieeexplore.ieee.org/document/10399282