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  • Remove data flange and disconnect all cables.  Mark out desired lengths and passivation locations for all data cables. Clear all cables to inside of vacuum box for power flange removal.
  • Disconnect patch panel. Remove power flange.  Implement final grounding scheme on power flange.
  • Remove all data cables for passivation and/or replacement.  Fold and passivate data cables.
  • Install temporary lever support.  Disconnect linear shifts and flex pivots.  Remove linear shifts. Disconnect cooling and remove cooling feedthroughs.
  • Release vacuum box from top clamp. Remove cooling manifold. Remove vacuum box for packing.
  • Pull FEB cooling plate out as far as L1-3 allows. Remove P4 male DB44 from patch panel and cut all zip ties on those wires. Remove L4b LV mezzanine, if necessary. Replace lower-left pin and re-insert.  If pin doesn’t push in, then replace upper-left pin.  Otherwise; extract and mark all pins, replace upper left pin, reinsert all pins in new shell.  Reinstall P4 on patch panel.  Push cooling plate back into SVT box.  Use clamp to lock patch panel into SVT box. Use zip ties to lock lever lock into place?
  • Re-install L4-6 data cables. Re-install L1-3 data cables, if possible. 
  • Install hall probe in L6 electron-side window with DP190 and tape wire into place.
  • Secure loose data cables in SVT box. Tape foil to box from crane straps.
  • Lock lever lock into box for safety with clamp.
  • Lock L46 upper hanger with jam nut!
  • Blow out cooling lines.
  • Prepare G10 pieces for SVT isolation.
  • Pack all needed items to take to Hall B for installation.
  • Prepare straps and tie-downs for lifts on Monday.
  • Move DAQ to Hall B and set up on network.
Plan for Monday:
  • Wipe down shipping plate from larger box and take into cleanroom on dollies. Lay foil along shipping plate for bottom of box. (15")
  • Release SVT from table.
  • Crane SVT onto shipping plate. (15")
  • Wrap and tape SVT box with foil. (15")
  • Roll SVT out of cleanroom. Cinch SVT down to shipping plate with tie downs. (15”)  *1’*
  • Install lid on inner box. (15")
  • Roll SVT out to crane area. (15")
  • Crane SVT into outer box.  Install foam. (15")
  • Close outer box. (15")
  • Crane outer box onto truck, levers facing rear, along with vacuum box and large crate with other items. (30”) *2’15”*
  • Slow truck move into Hall B down ramp. (30")
  • Crane inner box out. (15”) *3’*
  • Open inner box. (15")
  • Crane SVT up to pie tower on shipping plate. (15")
    • Pull SVT in and lower onto lift cart.
  • Move SVT to PS magnet (15")
    • Slow roll on lift cart to alcove.
    • Release SVT from shipping plate.
    • Transfer to lift cart/table in alcove.
    • Lift up on cart, then shoulder-height lift to table in front of vacuum chamber.
  • Get SVT into position to transfer to vacuum chamber (15”) *4’*
  • Transfer SVT to vacuum chamber. (15”) *4’15*
  • Isolate SVT box with G10 (15’)
  • Align SVT and lock into place (120")
Questions:
  • How heavy is the SVT?  Can we avoid the first crane lift with a manual lift?
  • Can we do to alignment on Day 1?

 

  • Noise performance results from run 855 with all dpms.  Noise looks as expected for all hybrids. 

==============================================================
Physical FEB: 1t Serial: FebFpga: 2
==============================================================
Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels.  Noise looks slightly higher but it's hard to tell
Hybrid 1: Looks fine. Noise ~55 ADC Counts, high noise on edge channels.  
==============================================================

==============================================================
Physical FEB: 2-3t Serial: FebFpga: 0
==============================================================
Hybrid 3: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 1: Looks fine. Noise ~54 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~52 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 4t Serial: FebFpga: 5
==============================================================
Hybrid 3: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 5t Serial: FebFpga: 8
==============================================================
Hybrid 3: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 6t Serial: FebFpga: 7
==============================================================
Hybrid 3: Looks fine. Noise ~53 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~54 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~53 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 1b Serial: FebFpga: 9
==============================================================
Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~53 ADC Counts, high noise on edge channels and noise rise on APV 0  
==============================================================

==============================================================
Physical FEB: 2-3b Serial: FebFpga: 6
==============================================================
Hybrid 3: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 4b Serial: FebFpga: 1
==============================================================
Hybrid 3: Looks fine. Noise ~52 ADC Counts, high noise on edge channels 
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels 
==============================================================

=============================================================
Physical FEB: 5b Serial: FebFpga: 4
==============================================================
Hybrid 3: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~49 ADC Counts, high noise on edge channels 
==============================================================

==============================================================
Physical FEB: 6b Serial: FebFpga: 3
==============================================================
Hybrid 3: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
==============================================================

  •  The SVT Gui was updated such that FebFpga 11 is now mapped to FebFpga 6.  This was needed in order for the EPICS hybrid and FEB temperature GUI's to function properly. 
  • A "power all" button was added to the hybrid GUI
  • FEB 23b and 5t were loaded with new firmware.  Data with these two boards will be taken tomorrow.  If the baseline and noise are found to be unreasonable, all boards will be flashed with the new firmware.

2015-02-15

  • Flashed the The remaining (8) FEB's were flashed with new firmware (0xD000000) firmware image 0xD0000000.  Ben or Ryan can provide a list of fixes/improvements that this version of the firmware contains.
  • The FEB's were powered on, and the links were all checked.  A Power up FEB's to check the links and saw a large amount of errors were immediately seen on  DPM 3/Data Path 0-2 and DPM 0, DP 0 and DPM 3, DP 1.  /Data Path 0.  The first group of links that had errors were all associated with the same FEB.  It's harder to tell if this is the case with the errors on DPM 0/Data Path 0.
  • Two fibers  (F & H)  were switched at the back of the COB in order to check if the link errors followed the DPM.  After the switch, the link errors were observed on DPM 10/Data Path 0-2.  This is where they were expected to appear if the errors were due to something downstream of the DPM.  This eliminated the DPM as being the cause of the link errors.
  • After switching the fibers at the back of the COB back to their original position, the same fibers were switched at the flange.  Once again, the errors showed up on DPM 10/DP 0-2.  This eliminated the fibers from being the problem.
  • The problematic links were then traced to FEB 6b.  In order to check if the problem was originating upstream of the FEB's, high speed cables 6b and 6t were switched. This was done through the side windows on the SVT box and was relatively easy to do. When this was done, the errors began to appear on DPM 5/6, which were the DPM's that were connected to 6t before the switch.  This seems to indicate that the link problems were originating from the FEB and not upstream.  We switched back the high speed cables to their original state.
  •  Finally, we switched the high speed cables connected to 6b and 6t at the flange.  Once again, we saw the same behavior observed during 5 above. This confirms that the link errors were being generated by the FEB's.
  • The system was let run for a few hours and the links were logged in order to check long term stability.


2015-02-16

New GUI to check hybrid sync status is now active:  svtHybSync.adl. 
It now contains information about the sync status for the FEBs. It looks like it’s working: I can see that the powered FEB right now has sync 0x0 for all data paths. The other don’t have a “valid xml” which make sense. We can change the error codes later. Please look at this and tell me if this status corresponds to what your expect. Below the sync I have information about the data DPM’s. It will allow us to see the status and configuration of all DPM’s. I’m also adding the link errors to this GUI. It works but I have turned it off now as it’s too slow. I’ll be working on that tomorrow morning. (Pelle)

2015-02-23

Updated to SVT DAQ epics. Check out instruction on  EPICS Instructions. We are now running 14 data dpm , 1 control dpm and 2 dtm control IOCs in parallel.
Added FebNum/HybNum and run state monitoring in "svtHybSync.adl" GUI from data dpm to check mapping.
Added new GUI svtDataDpmLinkStatus.adl GUI to monitor link error. Got the RxFrameErrorCount implemented so far.