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S30XL-LESA/LDMX
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5:10pm
Omar found that one of the LV mezzanine card (L5t, bottom screw) was now connecting AGND to the FEB support plate. After debugging turns out that it was the edge of the high-speed mSAS cables that was conducting and touching components on the FEBs.
TKN - my notes on this
5:30pm
L4t and L4b power was swapped on the back of the breakout box (on the flange side). For reference this is patch panel P3 and thus S1 and S2 where swapped. Mapping power to FEBs is ok now.
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SVT chiller flow switch tested. Drained and refilled chiller in the process; level is just above 3/4, jug is empty. Chiller is running at stage 3 (we got a pressure trip at stage 4, which has not happened before - not sure why); this will be our normal setting. Estimated flow (based on pressure drop vs. flow switch trip) is 1.5 GPM. SVT chiller is connected to Wesley's EPICS stuff; work in progress.
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Physical FEB: 4t Serial: FebFpga: 5
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Hybrid 3: Looks fine. Noise ~51 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 2: Looks fine. Noise ~52 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 0: Looks fine. Noise ~51 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
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Physical FEB: 6b Serial: FebFpga: 3
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Hybrid 3: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
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2015-02-13
2015-02-13
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Physical FEB: 1t Serial: FebFpga: 2
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Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels. Noise looks slightly higher but it's hard to tell
Hybrid 1: Looks fine. Noise ~55 ADC Counts, high noise on edge channels.
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Physical FEB: 2-3t Serial: FebFpga: 0
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Hybrid 3: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 1: Looks fine. Noise ~54 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
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Physical FEB: 4t Serial: FebFpga: 5
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Hybrid 3: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels and noise rise on APV 0, hump in noise of APV 0
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
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Physical FEB: 5t Serial: FebFpga: 8
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Hybrid 3: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
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Physical FEB: 6t Serial: FebFpga: 7
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Hybrid 3: Looks fine. Noise ~53 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~54 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~53 ADC Counts, high noise on edge channels
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Physical FEB: 1b Serial: FebFpga: 9
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Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~53 ADC Counts, high noise on edge channels and noise rise on APV 0
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Physical FEB: 2-3b Serial: FebFpga: 6
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Hybrid 3: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~55 ADC Counts, high noise on edge channels
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Physical FEB: 4b Serial: FebFpga: 1
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Hybrid 3: Looks fine. Noise ~52 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
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Physical FEB: 5b Serial: FebFpga: 4
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Hybrid 3: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~49 ADC Counts, high noise on edge channels
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Physical FEB: 6b Serial: FebFpga: 3
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Hybrid 3: Looks fine. Noise ~54 ADC Counts, high noise on edge channels and noise rise on APV 0
Hybrid 2: Looks fine. Noise ~50 ADC Counts, high noise on edge channels
Hybrid 1: Looks fine. Noise ~51 ADC Counts, high noise on edge channels
Hybrid 0: Looks fine. Noise ~50 ADC Counts, high noise on edge channels and noise rise on APV 0
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2015-02-15
2015-02-16
New GUI to check hybrid sync status is now active: svtHybSync.adl.
It now contains information about the sync status for the FEBs. It looks like it’s working: I can see that the powered FEB right now has sync 0x0 for all data paths. The other don’t have a “valid xml” which make sense. We can change the error codes later. Please look at this and tell me if this status corresponds to what your expect. Below the sync I have information about the data DPM’s. It will allow us to see the status and configuration of all DPM’s. I’m also adding the link errors to this GUI. It works but I have turned it off now as it’s too slow. I’ll be working on that tomorrow morning. (Pelle)
2015-02-23
Updated to SVT DAQ epics. Check out instruction on EPICS Instructions. We are now running 14 data dpm , 1 control dpm and 2 dtm control IOCs in parallel.
Added FebNum/HybNum and run state monitoring in "svtHybSync.adl" GUI from data dpm to check mapping.
Added new GUI svtDataDpmLinkStatus.adl GUI to monitor link error. Got the RxFrameErrorCount implemented so far.