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s3df: /sdf/data/lcls/drpsrcf/ffb/tst/tstx00417/xtc/ request Wilko to synchronize with psdm?

Geometry

Panel geometry

  • size of the ASIC is 192*384
  • epixm panel: raw shape:(1, 384, 768) or: (384, 4*192)
  • 50um x 50um pixels, no wide pixels

Data on pslogin > dubrovin@drp-neh-cmp001

       ssh -Y drp-neh-cmp001
       datinfo -k exp=tstx00417,run=324,dir=/drpneh/data/tst/tstx00417/xtc -d epixm
       epixm320_dark_proc -k exp=tstx00417,run=324,dir=/drpneh/data/tst/tstx00417/xtc/ -d epixm -o ./work -D

Raw shape: (4, 192, 384)

Geometry

Panel geometry

  • ASIC shape (192,384)
  • epixm panel: raw shape:(4, 384, 768)
  • 50um x 50um pixels, no wide pixels
Code Block
title2024-03-18 e-mail exchange about epixm panel geometry
collapsetrue
O'Grady, Paul Christopher
Tue 3/19/2024 8:46 AM
Good to know … thanks for the clarification, Chris. chris
Kenney, Christopher J. <kenney@slac.stanford.edu>
O'Grady, Paul Christopher
Alnajjar, Dawood;
​Doering, Dionisio
Code Block
title2024-03-18 e-mail exchange about epixm panel geometry
collapsetrue
O'Grady, Paul Christopher
Tue 3/19/2024 8:46 AM
Good to know … thanks for the clarification, Chris. chris
Kenney, Christopher J. <kenney@slac.stanford.edu>
O'Grady, Paul Christopher
Alnajjar, Dawood;
​Doering, Dionisio;
​Claus, Ric;
​Dubrovin, Mikhail
​
Hi Chris,
Your assumption has always been correct - until now.
For ePixM each detector is composed of four mechanically separate chip pairs. 
These ASIC-"sensor" pairs are significantly more complex and hence risky and may have lower yield. These
"sensors" are also limited in size to one lithographic reticle field. 
Sorry.  But ePixM will need metrology. 
Thanks,
Chris
O'Grady, Paul Christopher <cpo@slac.stanford.edu>
​
Kenney, Christopher J.
​Alnajjar, Dawood;
​Doering, Dionisio;
​Klaus, Ric;
​Dubrovin, Mikhail
​
Hi Chris,
Just to check: I had the impression these units of 4 asics (whether in a square or in a line) should be one solid piece of silicon which shouldn’t need metrology.  Do I misunderstand?
chris

Kenney, Christopher J. <kenney@slac.stanford.edu>
​Alnajjar, Dawood;
​O'Grady, Paul Christopher;
​Doering, Dionisio
​Claus, Ric;
​Dubrovin, Mikhail
​
HI Mikhail,
I've performed a metrology on a module and will provide you with the file this week.
Thanks,

Chris
Alnajjar, Dawood <dnajjar@slac.stanford.edu>
​O'Grady, Paul Christopher;
​Kenney, Christopher J.;
​Doering, Dionisio
​Claus, Ric;
​Dubrovin, Mikhail
​
Hi Mikhail & Chris,
Thanks for reaching out. The Pixel size is 50um x 50um, and we assume no large pixels at this point. Also there are no gaps between pixels. 
@Kenney, Christopher J. would you know if there are gap between the ASICs?
Thanks,
Dawood

Alnajjar, Dawood <dnajjar@slac.stanford.edu>
​O'Grady, Paul Christopher <cpo@slac.stanford.edu>;
​Kenney, Christopher J.;
​Doering, Dionisio
​Claus, Ric;
Dubrovin, Mikhail
​
Hi Mikhail & Chris,
The Pixel size is 50um x 50um, and we assume no large pixels at this point. Also there are no gaps between pixels. 
@Kenney, Christopher J. would you know the gap between the ASICs?
Thanks,
Dawood

2024-03-18 11:18am
O'Grady, Paul Christopher <cpo@slac.stanford.edu>
​Kenney, Christopher J.;
​Doering, Dionisio;
​Alnajjar, Dawood
Claus, Ric;
​Dubrovin, Mikhail
​
Chris K., Dionisio, Dawood,
Could you send Mikhail the geometry for the 4 asic epixm panel?  He needs to know pixel sizes (including things like “large pixels”) and any gaps between pixels/asics.
Thanks!
chris

Gain

Configuration info for gain (from Lorenzo Rota gain modes) for AHL, FH, SM

...

/asics.
Thanks!
chris

Gain

Configuration info for gain (from Lorenzo Rota gain modes) for AHL, FH, SM

ModeCompTH_ePixMPrecharge_DAC_ePixM
Auto-gain1245
Fixed High045
Soft Low6350

Gain and data bits

15 data bits: 0x7fff or 0o77777

16-th gain bit: 0x8000 or 0o100000

gain bit: 0/1 - high/low gain mode

Calibration constants

Geometry deployment

Code Block
titlecurrent version of the default geometry, orientation of ASICs is not guaranteed
collapsetrue
# HDR PARENT IND        OBJECT IND     X0[um]   Y0[um]   Z0[um]   ROT-Z ROT-Y ROT-X     TILT-Z   TILT-Y   TILT-X

SEGMENT        0    EPIXMASIC:V1  0     -9600     4800        0     180     0     0    0.00000  0.00000  0.00000
SEGMENT        0    EPIXMASIC:V1  1      9600     4800        0     180     0     0    0.00000  0.00000  0.00000
SEGMENT        0    EPIXMASIC:V1  2      9600    -4800        0       0     0     0    0.00000  0.00000  0.00000
SEGMENT        0    EPIXMASIC:V1  3     -9600    -4800        0       0     0     0    0.00000  0.00000  0.00000
IP             0    SEGMENT       0         0        0    10000      90     0     0    0.00000  0.00000  0.00000


  • by default: lcls2/psana/psana/pscalib/geometry/data/geometry-def-epixm320.data
  • cdb add -e tstx00417 -d epixm320_0016777984-4294967295-4294967295-4032267777-3204448280-0177427457-3053453334 -c geometry -r 309 -f geometry-def-epixm320.data -i txt

Dark processing and deployment

  • epixm320_dark_proc -k exp=tstx00417,run=324,dir=/drpneh/data/tst/tstx00417/xtc/ -d epixm -o ./work -D
  • dark run should have 3 steps for gains SH, SL, AHL
  • raw (4-ASIC) panel shape: (4, 192, 384)
  • constants are saved in repository (see location using command epixm320_dark_proc -h) per panel per gain range
  • -D option combines gain ranges constants for pedestals, pixel_status, pixel_rms, pixel_min, pixel_max in shape (3, 4, 192, 384) and deploys them in the DB

Gain from charge injection

  • TBD

...

References