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SLAC Register Protocol (SRP)
Pretty Good Protocol (PGP)
ASIC Protocols
Line Codes
Slac Streaming Protocol (SSP)
Packetizers & Chunkers
- AxiStream Packetizer Protocol Version 0
- AxiStream Packetizer Protocol Version 2
- AxiStream Batcher Protocol Version 1
Network Protocols
Misc. Protocols
SRP Version 0
Incoming Request
| Word# | BITS | Name | Description | Note |
|---|---|---|---|---|
| 0 | [31:0] | TID[31:0] | Transaction ID | (echoed back) |
| 1 | [29:0] | Address[31:2] | Start Address | Always 32-bit aligned |
| 1 | [31:30] | OP-Code | Operation Code | 0x0=Read, 0x1=Write,
|
| 2 | [31:0] | WriteData[31:0] or ReadCount[8:0] | First Write or Read request counter | Up to 2^9 words per transactions |
| ... | ... | ... | ... | |
| N-1 | [31:0] | WriteData[31:0] | Last Write | |
| N | [31:0] | Don't Care | Don't Care |
Outgoing Response
| Word# | BITS | Name | Description | Note |
|---|---|---|---|---|
| 0 | [31:0] | TID[31:0] | Transaction ID | (echoed back) |
| 1 | [29:0] | Address[31:2] | Start Address | Always 32-bit aligned |
| 1 | [31:30] | OP-Code | Operation Code | 0x0=Read, 0x1=Write,
|
| 2 | [31:0] | WriteData[31:0] or ReadData[31:0] | First Write or First Read | |
| ... | ... | ... | ... | |
| N-1 | [31:0] | WriteData[31:0] or ReadData[31:0] | Last Write or Last Read | |
| N | [0] | Fail Flag | Register transaction Error | (response data) |
| N | [1] | Timeout Flag | Timeout Error | (response data) |
| N | [31:2] | Reserved | Reserved (0x0) | Reserved for Future Use |
Note: "set" and "clear" were defined but never implemented in the software and firmware.
SRP Version 1
Contact Till Straumann <strauman@slac.stanford.edu> for SRP version 1 definition
SRP Version 2
Contact Till Straumann <strauman@slac.stanford.edu> for SRP version 2 definition
Memory Access Protocol (MAP) ¯\_(ツ)_/¯
Incoming Request
| Word# | BITS | Name | Description | Note |
|---|---|---|---|---|
| 0 | [31:0] | TID[31:0] | Transaction ID | (echoed back) |
| 0 | [31:0] | TID[63:32] | Transaction ID | (echoed back) |
| 1 | [29:0] | Size | Number of 32-bit words to transfer | |
| 1 | [31:30] | Unused | ||
| 2 | [30:0] | Address[33:2] | Starting word address of transfer | Bits 1:0 are always 0 |
| 2 | [31] | RNW | OpCode | 0=Read, 1=Write |
Outgoing Response
| Word# | BITS | Name | Description | Note |
|---|---|---|---|---|
| 0 | [31:0] | TID[31:0] | Transaction ID | (echoed back) |
| 0 | [31:0] | TID[63:32] | Transaction ID | (echoed back) |
| 1 | [29:0] | Size | Number of 32-bit words to transfer | |
| 1 | [31:30] | Unused | ||
| 2 | [30:0] | Address[33:2] | Starting word address of transfer | Bits 1:0 are always 0 |
| 2 | [31] | RNW | OpCode | 0=Read, 1=Write |
| 3+N | Data | Read data word N | ||
| 3+N+Size | [0] | Error | An error occured | |
| 3+N+Size | [2:1] | ErrorValue | AXI Return code |
SRP Version 3
Requirements
- Support an AXI4-Lite and AXI4 firmware modules
- SrpV3AxiLite.vhd will only support 32-bit transactions and 32-bit alignment
- For applications that need non 32-bit transactions or non 32-bit alignment for AXI-Lite, we can achieve this by bridging the SrpV3Axi.vhd with the AxiToAxiLite.vhd
- Echos back the AXI stream's TDEST
- Header will include:
- SRP Version number: (8-bits)
- Always echo backs the local version
- OP-Code: Non-Posted Read, Non-Posted Write, Posted Write, NULL (2-bit)
- Spare (6-bit)
- Retry counter (8-bit)
- Timeout counter (8-bit)
- In units of 100 ms
- If 0x0, no time out
- Transaction ID: (32-bits)
- Base Address of bursting (64-bits)
- Request Size (32-bit)
- In units of bytes
- Max. read size is 232
- Max. write size is 212
- SRP Version number: (8-bits)
- Header will be echoed except for:
- SRP Verson number
- Footer will be 32-bit, zero on success, and will include:
- Memory Bus response (8-bit)
- success == 0x0
- failed != 0x0
- Timeout flag (1-bit)
- Request's EOFE (1-bit)
- Version Mismatch (1-bit)
- Invalid request size (1-bit)
- All other bits must be 0x0
- Memory Bus response (8-bit)
- 32-bit data register transactions
- Byte aligned access
- Read and Write transactions supported
- Set and Clear transactions NOT supported
- Read Modify Write NOT supported
- 64-bit address space
- 64-bit required for >4 GB DDR memory
- Support single and bursting transactions
- Support up to 232 byte read burst transactions
- Support up to 212 byte write burst transactions
- Only support contiguous bursting
- If inbound request (non-posted) is received and EOFE, the SRP firmware will not perform read/write transaction and respond back.
- Requires caching up the transaction (Set AxiStreamFifo's VALID_THOLD_G = 0)
- While caching: If the FIFO is full and no request frame detected (SOF + EOF), then the SRP firmware will drain the FIFO
- If inbound request is received with version number not equal to the protocol, the SRP firmware will not perform read/write transaction and respond back
Incoming Request
| Word# | BITS | Name | Description | Note |
|---|---|---|---|---|
| 0 | [7:0] | Version[7:0] | SRP Version number | |
| 0 | [9:8] | OpCode[1:0] | Operation Code |
|
| 0 | [15:10] | SPARE[5:0] | Unused, spare bits | |
| 0 | [23:16] | RetryCnt[7:0] | Retry Counter | |
| 0 | [31:24] | TimeoutCnt[7:0] | Timeout Counter |
|
| 1 | [31:0] | TID[31:0] | Transaction ID | |
| 2 | [31:0] | Addr[31:0] | Register Address | In units of bytes |
| 3 | [31:0] | Addr[63:32] | Register Address | In units of bytes |
| 4 | [31:0] | ReqSize[31:0] | Request Size |
|
| 5 | [31:0] | WriteData[31:0] | Write Data | Only used for write operations |
| ... | ... | ... | ... | Only used for write operations |
| 4+CEIL((ReqSize+1)/4) | [31:0] | WriteData[31:0] | Write Data | Only used for write operations |
Outgoing Response
...
- if MemResp == 0, then success
- if MemResp != 0, then failed
...
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