A simple ASCII protocol for memory reads and writes over a UART interface.
The firmware implementation is here:
https://github.com/slaclab/surf/blob/master/protocols/uart/rtl/UartAxiLiteMaster.vhd
The software implementation is here:
https://github.com/slaclab/rogue/blob/master/python/pyrogue/protocols/_uart.py
The format is as follows:
Write
Send
w|W ADDRHEX DATAHEX \r|\n
Response
w|W ADDRHEX DATAHEX RESPCODE \r|\n
Read
Send:
r|R ADDRHEX \r|\n
Response:
r|R ADDRHEX DATAHEX \r|\n
Blank lines ignored
Extra words ignored
Contact
Ben Reese
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