I/O needs
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
GT transceiver signals
The FPGA has two types of GT quads:
- GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
- 8 quads with 4 TX/RX in each for a total of 32 transceivers
- GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
- 11 quads with 4 TX/RX in each for a total of 44 transceivers
LEAP transceivers
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
ASICs
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
- 6*8=48 RX channels
- 6*1=6 TX channels
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
Total data rates
- 6x ASICs, 8x data outputs per ASIC, up to 6 Gbit/s per data output: 6*8*6=288 Gbit/s
- 12x LEAP transceiver channels up to 25 Gbit/s:
- 1 channel will be used for timing?
- Data rate left: 11*25=275 Gbit/s
- 275/(6*8) ≈ 5.7 Gbit/s per ASIC in this case (+encoding)
- Running PGPv4 at 25 Gbit/s has not been proven yet!
From FPGA to PC:
- 168*192*12(bit)*66/64(PGP encoding) = 399168 bits/frame/ASIC
- @35 kHz frame rate: 6*399168*35e3 = 83.82528 Gbit/s ≈ 83.8 Gbit/s
- 83.82528/11 = 7.62048 Gbit/s ≈ 7.6 Gbit/s per LEAP channel (11 channels in total)
- @100 kHz frame rate: 6*399168*100e3 = 239.5008 Gbit/s ≈ 239.5 Gbit/s
- 239.5008/11 = 21.7728 Gbit/s ≈ 21.8 Gbit/s per LEAP channel (11 channels in total)
Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:
- 11 channels at 15 Gbit/s: 11*15*64/66(PGP encoding) = 160 Gbit/s
- 6 ASICs: 160/6*12/14(encoding) = 22.85714286 ≈ 22.9 Gbit/s per ASIC
- 22.9/8 = 2.8625 Gbit/s per data output
- 22.85714286e9/(168*192*12) = 59051.39834449 ≈ 59 kHz frame rate
GT reference clocks
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and purple/blue):
- One for the LEAP channels for the GTY quads 0 to 2
- One for the ASIC clock channels for the GTY quads 4 and 5
- One for the ASIC data channels for the GTY quads 6 and 7
- One for the ASIC data channels for the GTH quads 0 to 4
- One for the ASIC data channels for the GTH quads 5 to 9
This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview above for more details on the system clock structure.
Note |
---|
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s" |
Summary
| Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 |
---|
| TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX |
---|
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP |
|
| N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C |
|
|
|
|
|
|
---|
Clock | |← | ← X → | →| |
| | X → | →| | | X → | →| |
|
|
|
---|
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC |
|
|
---|
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
|
---|
There is one GTY quad and one GTH quad left over.
← ePixUHR35kHz - Megapixel Cameras
Useful resources
Image Removed
Image Removed
Table of contents
...
...
Table of contents
...
Components
...
...
FPGA
...
- Package mechanical drawing
- FPGA measured 3D model
- Difference between the drawing and 3D model used:
- Total height (A = A1 + A2):
- 3D model is 3.86 mm
- Drawing is 3.71 mm (max)
- Solder ball height (A1):
- 3D model is 0.6 mm
- Drawing is 0.6 mm (max)
- Package height (A2):
- 3D model is 3.26 mm
- Drawing is 3.21 mm (max)
- → It seems that the 3D model of the package we have is not 100% accurate, but the difference (3.86-3.71=0.15 mm) is negligible
- Any thermal interface between the package and the cooling block should be able to "absorb" this difference
...
DC/DC converters
...
Clocks
...
Timing
...
displayName | clock-diagram |
---|
name | clock-diagram |
---|
pagePin | 10 |
---|
ADC/DAC
Temperature
- One on carrier board going to ADC
- One on
Timing
Is external electrical timing needed?
ADC/DAC
How many ADC channels are needed?
Do we need a high-speed ADC?
Temperature
NHQM103B375T10 10k NTC type thermistors are used at:
- One on carrier board going to ADC
- One on readout board going to the ADC
- One on carrier board going to external connector?
Humidity
...
LDO monitoring
ASIC monitoring
LDOs
Various peripherals
ID
A DS2411R+T&R chip is located on the readout board to provide a unique ID that can be read out by the FPGA. Another ID chip is also place on the carrier board.
Flash
Used to store the FPGA configuration.
EEPROM
Used to store operational settings and parameters.
JTAG
A 14-pin JTAG connector (Molex 87832-1420) is located at the bottom of the readout board to not interfere with the cold plate on the top.
Block diagram
Gliffy Diagram |
---|
displayName | 3x2-readout-board-overview |
---|
name | 3x2-readout-board-overview |
---|
pagePin | 16 |
---|
|
Power
- Busbars for input power or TFM connector?
Different options for power components
Gliffy Diagram |
---|
displayName | power-components-info |
---|
name | power-components-info |
---|
pagePin | 3 |
---|
|
...
Image Removed
...
FPGA
https://www.xilinx.com/products/technology/power/xpe.html
ASICs
ePixUHR Throughput Calculations
From ASIC to FPGA:
- 168*192*12(bit)*14/12(encoding) = 451584 bits/frame
- @35 kHz frame rate: 451584 bits/frame * 35 kHz = 15.8 Gbit/s per ASIC
- 15.8/8=1.975 Gbit/s per data output
- @100 kHz frame rate: 451584 bits/frame * 100 kHz = 45.2 Gbit/s per ASIC
- 45.2/8=5.65 Gbit/s per data output
Power
- ASIC Version 2 - 2023: ePixUHR-100kHz: power consumption ← Using these numbers in the table below
- ASIC Version 1 - 2022: ePixUHR: power consumption
...
Analog
...
Digital and I/O
...
Analog test system
...
Net
...
G_AS
...
G_DS
...
G_AS_2V5
...
Voltage
...
1.3 V
...
1.3V
...
2.5 V
...
Required current per ASIC
...
1.85 A ≈ 1.9 A
...
0.468 A ≈ 0.5 A
...
0.01 A
...
System requirement with 6 ASICs
(adding +30% current for PVT variation)
...
6*1.9*1.3=14.82 A
+1.3 V @ 15 A
1.3*15=19.5 W
...
6*0.5*1.3=3.9 A
+1.3 V @ 4.0 A
1.3*4=5.2 W
...
6*0.01*1.3=0.078 A
+2.5 V @ 0.5 A
2.5*0.5=1.25 W
Power block diagram
TODO
Gliffy Diagram |
---|
size | 300 |
---|
displayName | power-block-diagram |
---|
name | power-graph |
---|
pagePin | 10 |
---|
|
I/O needs
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
GT transceiver signals
The FPGA has two types of GT quads:
- GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
- 8 quads with 4 TX/RX in each for a total of 32 transceivers
- GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
- 11 quads with 4 TX/RX in each for a total of 44 transceivers
LEAP transceivers
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
ASICs
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
- 6*8=48 RX channels
- 6*1=6 TX channels
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
Total data rates
- 6x ASICs, 8x data outputs per ASIC, up to 6 Gbit/s per data output: 6*8*6=288 Gbit/s
- 12x LEAP transceiver channels up to 25 Gbit/s:
- 1 channel will be used for timing?
- Data rate left: 11*25=275 Gbit/s
- 275/(6*8) ≈ 5.7 Gbit/s per ASIC in this case (+encoding)
- Running PGPv4 at 25 Gbit/s has not been proven yet!
From FPGA to PC:
- 168*192*12(bit)*66/64(PGP encoding) = 399168 bits/frame/ASIC
- @35 kHz frame rate: 6*399168*35e3 = 83.82528 Gbit/s ≈ 83.8 Gbit/s
- 83.82528/11 = 7.62048 Gbit/s ≈ 7.6 Gbit/s per LEAP channel (11 channels in total)
- @100 kHz frame rate: 6*399168*100e3 = 239.5008 Gbit/s ≈ 239.5 Gbit/s
- 239.5008/11 = 21.7728 Gbit/s ≈ 21.8 Gbit/s per LEAP channel (11 channels in total)
Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:
- 11 channels at 15 Gbit/s: 11*15*64/66(PGP encoding) = 160 Gbit/s
- 6 ASICs: 160/6*12/14(encoding) = 22.85714286 ≈ 22.9 Gbit/s per ASIC
- 22.9/8 = 2.8625 Gbit/s per data output
- 22.85714286e9/(168*192*12) = 59051.39834449 ≈ 59 kHz frame rate
GT reference clocks
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and purple/blue):
- One for the LEAP channels for the GTY quads 0 to 2
- One for the ASIC clock channels for the GTY quads 4 and 5
- One for the ASIC data channels for the GTY quads 6 and 7
- One for the ASIC data channels for the GTH quads 0 to 4
- One for the ASIC data channels for the GTH quads 5 to 9
This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview above for more details on the system clock structure.
Note |
---|
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s" |
Summary
...
There is one GTY quad and one GTH quad left over.
← ePixUHR35kHz - Megapixel Cameras
Useful resources
Image Removed
Image Removed
Table of contents
Table of Contents |
---|
maxLevel | 2 |
---|
exclude | \b(?:Table of contents|Useful resources)\b|\* |
---|
|
Components
FPGA
The FPGA that will be used is XCKU15P-2FFVA1760E from AMD/Xilinx.
- Package mechanical drawing
- FPGA measured 3D model
- Difference between the drawing and 3D model used:
- Total height (A = A1 + A2):
- 3D model is 3.86 mm
- Drawing is 3.71 mm (max)
- Solder ball height (A1):
- 3D model is 0.6 mm
- Drawing is 0.6 mm (max)
- Package height (A2):
- 3D model is 3.26 mm
- Drawing is 3.21 mm (max)
- → It seems that the 3D model of the package we have is not 100% accurate, but the difference (3.86-3.71=0.15 mm) is negligible
- Any thermal interface between the package and the cooling block should be able to "absorb" this difference
Optical transceiver
DC/DC converters
12V vs 24V (GT readout platform) vs 48V (TXI) input?
Clocks
Gliffy Diagram |
---|
displayName | clock-diagram |
---|
name | clock-diagram |
---|
pagePin | 10 |
---|
|
Timing
Is external electrical timing needed?
ADC/DAC
How many ADC channels are needed?
Do we need a high-speed ADC?
Temperature
NHQM103B375T10 10k NTC type thermistors are used at:
- One on carrier board going to ADC
- One on readout board going to the ADC
- One on carrier board going to external connector?
Humidity
One HIH-5031-001 sensor mounted close to the carrier connector.
LDO monitoring
ASIC monitoring
LDOs
Various peripherals
ID
A DS2411R+T&R chip is located on the readout board to provide a unique ID that can be read out by the FPGA. Another ID chip is also place on the carrier board.
Flash
Used to store the FPGA configuration.
EEPROM
Used to store operational settings and parameters.
JTAG
A 14-pin JTAG connector (Molex 87832-1420) is located at the bottom of the readout board to not interfere with the cold plate on the top.
Block diagram
Gliffy Diagram |
---|
displayName | 3x2-readout-board-overview |
---|
name | 3x2-readout-board-overview |
---|
pagePin | 16 |
---|
|
Power
- Busbars for input power or TFM connector?
Different options for power components
Gliffy Diagram |
---|
displayName | power-components-info |
---|
name | power-components-info |
---|
pagePin | 3 |
---|
|
...
Gliffy Diagram |
---|
size | 300 |
---|
displayName | power-supply-option-b |
---|
name | power-supply-option-b |
---|
pagePin | 4 |
---|
|
FPGA
https://www.xilinx.com/products/technology/power/xpe.html
ASICs
ePixUHR Throughput Calculations
From ASIC to FPGA:
- 168*192*12(bit)*14/12(encoding) = 451584 bits/frame
- @35 kHz frame rate: 451584 bits/frame * 35 kHz = 15.8 Gbit/s per ASIC
- 15.8/8=1.975 Gbit/s per data output
- @100 kHz frame rate: 451584 bits/frame * 100 kHz = 45.2 Gbit/s per ASIC
- 45.2/8=5.65 Gbit/s per data output
Power
- ASIC Version 2 - 2023: ePixUHR-100kHz: power consumption ← Using these numbers in the table below
- ASIC Version 1 - 2022: ePixUHR: power consumption
...
Analog
...
Digital and I/O
...
Analog test system
...
Net
...
G_AS
...
G_DS
...
G_AS_2V5
...
Voltage
...
1.3 V
...
1.3V
...
2.5 V
...
Required current per ASIC
...
1.85 A ≈ 1.9 A
...
0.468 A ≈ 0.5 A
...
0.01 A
...
System requirement with 6 ASICs
(adding +30% current for PVT variation)
...
6*1.9*1.3=14.82 A
+1.3 V @ 15 A
1.3*15=19.5 W
...
6*0.5*1.3=3.9 A
+1.3 V @ 4.0 A
1.3*4=5.2 W
...
6*0.01*1.3=0.078 A
+2.5 V @ 0.5 A
2.5*0.5=1.25 W
Power block diagram
TODO
Gliffy Diagram |
---|
size | 300 |
---|
displayName | power-block-diagram |
---|
name | power-graph |
---|
pagePin | 10 |
---|
|
I/O needs
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
GT transceiver signals
The FPGA has two types of GT quads:
- GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
- 8 quads with 4 TX/RX in each for a total of 32 transceivers
- GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
- 11 quads with 4 TX/RX in each for a total of 44 transceivers
LEAP transceivers
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
ASICs
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
- 6*8=48 RX channels
- 6*1=6 TX channels
This is more than what is available in GTH or GTY separately, which means that some ASIC GT channels will be in GTH and some in GTY. It would also be beneficial to have the TX and RX channels separated to avoid constraining the resources and there are enough FPGA GTs available for this. As shown in the table below, there are 8x ASIC RX channels that are placed in two GTY quads.
Total data rates
...
- 1 channel will be used for timing?
- Data rate left: 11*25=275 Gbit/s
- 275/(6*8) ≈ 5.7 Gbit/s per ASIC in this case (+encoding)
- Running PGPv4 at 25 Gbit/s has not been proven yet!
Flash
EEPROM
JTAG
Block diagram
Power
- Busbars for input power or TFM connector?
Different options for power components
Option A Same components as used in the GT readout platform | Option B New components with PMBUS capability |
---|
Image Added
| Gliffy Diagram |
---|
| |
---|
size | 300 |
---|
displayName | power-supply-option-b |
---|
name | power-supply-option-b |
---|
pagePin | 2 |
---|
|
|
FPGA
ASICs
ePixUHR Throughput Calculations
- 168*192*12(bit)*14/12(encoding) = 451584 bits/frame
- @35 kHz frame rate: 451584 bits/frame * 35 kHz = 15.8 Gbit/s per ASIC
- 15.8/8=1.975 Gbit/s per data output
- @100 kHz frame rate: 451584 bits/frame * 100 kHz = 45.2 Gbit/s per ASIC
- 45.2/8=5.65 Gbit/s per data output
Power
- ASIC Version 2 - 2023: ePixUHR-100kHz: power consumption ← Using these numbers in the table below
- ASIC Version 1 - 2022: ePixUHR: power consumption
| Analog | Digital and I/O | Analog test system |
---|
Net | G_AS | G_DS | G_AS_2V5 |
---|
Voltage | 1.3 V | 1.3V | 2.5 V |
---|
Required current per ASIC | 1.85 A ≈ 1.9 A | 0.468 A ≈ 0.5 A | 0.01 A |
---|
System requirement with 6 ASICs (adding +30% current for PVT variation) | 6*1.9*1.3=14.82 A +1.3 V @ 15 A 1.3*15=19.5 W | 6*0.5*1.3=3.9 A +1.3 V @ 4.0 A 1.3*4=5.2 W | 6*0.01*1.3=0.078 A +2.5 V @ 0.5 A 2.5*0.5=1.25 W |
---|
Power block diagram
I/O needs
GT transceiver signals
- GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
- 8 quads with 4 TX/RX in each for a total of 32 transceivers
- GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
- 11 quads with 4 TX/RX in each for a total of 44 transceivers
LEAP transceivers
ASICs
- 6*8=48 RX channels
- 6*1=6 TX channels
Total data rates
- 6x ASICs, 8x data outputs per ASIC, up to 6 Gbit/s per data output: 6*8*6=288 Gbit/s
- 12x LEAP transceiver channels up to 25 Gbit/s:
- 1 channel will be used for timing?
- Data rate left: 11*25=275 Gbit/s
- 275/(6*8) ≈ 5.7 Gbit/s per ASIC in this case (+encoding)
- Running PGPv4 at 25 Gbit/s has not been proven yet!
From FPGA to PC:
- 168*192*12(bit)*66/64(PGP encoding) = 399168 bits/frame/ASIC
- @35 kHz frame rate: 6*399168*35e3 = 83.82528 Gbit/s ≈ 83.8 Gbit/s
- 83.82528/11 = 7.62048 Gbit/s ≈ 7.6 Gbit/s per LEAP channel (11 channels in total)
- @100 kHz frame rate: 6*399168*100e3 = 239.5008 Gbit/s ≈ 239.5 Gbit/s
- 239.5008/11 = 21.7728 Gbit/s ≈ 21.8 Gbit/s per LEAP channel (11 channels in total)
- 11 channels at 15 Gbit/s: 11*15*64/66(PGP encoding) = 160 Gbit/s
- 6 ASICs: 160/6*12/14(encoding) = 22.85714286 ≈ 22.9 Gbit/s per ASIC
- 22.9/8 = 2.8625 Gbit/s per data output
- 22.85714286e9/(168*192*12) = 59051.39834449 ≈ 59 kHz frame rate
GT reference clocks
- One for the LEAP channels for the GTY quads 0 to 2
- One for the ASIC clock channels for the GTY quads 4 and 5
- One for the ASIC data channels for the GTY quads 6 and 7
- One for the ASIC data channels for the GTH quads 0 to 4
- One for the ASIC data channels for the GTH quads 5 to 9
Note |
---|
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s" |
Summary
| Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 |
---|
| TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX |
---|
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP |
|
| N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C |
|
|
|
|
|
|
---|
Clock | |← | ← X → | →| |
| | X → | →| | | X → | →| |
|
|
|
---|
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC |
|
|
---|
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
|
---|
Useful resources
Table of contents
Components
FPGA
- Package mechanical drawing
- FPGA measured 3D model
- Difference between the drawing and 3D model used:
- Total height (A = A1 + A2):
- 3D model is 3.86 mm
- Drawing is 3.71 mm (max)
- Solder ball height (A1):
- 3D model is 0.6 mm
- Drawing is 0.6 mm (max)
- Package height (A2):
- 3D model is 3.26 mm
- Drawing is 3.21 mm (max)
- → It seems that the 3D model of the package we have is not 100% accurate, but the difference (3.86-3.71=0.15 mm) is negligible
- Any thermal interface between the package and the cooling block should be able to "absorb" this difference
Optical transceiver
DC/DC converters
Clocks
Timing
ADC/DAC
Temperature
- One on carrier board going to ADC
- One on readout board going to the ADC
- One on carrier board going to external connector?
Humidity
LDO monitoring
ASIC monitoring
LDOs
Various peripherals
ID
Flash
EEPROM
JTAG
Block diagram
Power
- Busbars for input power or TFM connector?
Different options for power components
Option A Same components as used in the GT readout platform | Option B New components with PMBUS capability |
---|
Gliffy Diagram |
---|
| |
---|
chrome | min |
---|
size | 300 |
---|
displayName | power-supply-option-a |
---|
name | power-supply-options |
---|
pagePin | 53 |
---|
|
| Gliffy Diagram |
---|
size | 300 |
---|
displayName | power-supply-option-b |
---|
name | power-supply-option-b |
---|
pagePin | 4 |
---|
|
|
FPGA
ASICs
ePixUHR Throughput Calculations
...
- 168*192*12(bit)*6614/6412(PGP encoding) = 399168 451584 bits/frame/ASIC
- @35 kHz frame rate: 6*399168*35e3 = 83.82528 Gbit/s ≈ 83.8 Gbit/s
- 83.82528/11 = 7.62048 Gbit/s ≈ 7.6 Gbit/s per LEAP channel (11 channels in total)
- @100 kHz frame rate: 6*399168*100e3 = 239.5008 Gbit/s ≈ 239.5 Gbit/s
- 239.5008/11 = 21.7728 Gbit/s ≈ 21.8 Gbit/s per LEAP channel (11 channels in total)
Reverse calculation assuming the current PGPv4 running at 15 Gbit/s:
- 11 channels at 15 Gbit/s: 11*15*64/66(PGP encoding) = 160 Gbit/s
- 6 ASICs: 160/6*12/14(encoding) = 22.85714286 ≈ 22.9 Gbit/s per ASIC
- 22.9/8 = 2.8625 Gbit/s per data output
- 22.85714286e9/(168*192*12) = 59051.39834449 ≈ 59 kHz frame rate
GT reference clocks
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
In the table below there are the following reference clock inputs (marked with X and purple/blue):
- One for the LEAP channels for the GTY quads 0 to 2
- One for the ASIC clock channels for the GTY quads 4 and 5
- One for the ASIC data channels for the GTY quads 6 and 7
- One for the ASIC data channels for the GTH quads 0 to 4
- One for the ASIC data channels for the GTH quads 5 to 9
This means at least one reference clock is needed for the LEAP channels and four reference clocks are needed for the ASIC channels. See 3x2 readout board overview above for more details on the system clock structure.
Note |
---|
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s" |
Summary
...
There is one GTY quad and one GTH quad left over.
← ePixUHR35kHz - Megapixel Cameras
Useful resources
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Image Removed
Table of contents
Table of Contents |
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maxLevel | 2 |
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exclude | \b(?:Table of contents|Useful resources)\b|\* |
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Components
FPGA
The FPGA that will be used is XCKU15P-2FFVA1760E from AMD/Xilinx.
- Package mechanical drawing
- FPGA measured 3D model
- Difference between the drawing and 3D model used:
- Total height (A = A1 + A2):
- 3D model is 3.86 mm
- Drawing is 3.71 mm (max)
- Solder ball height (A1):
- 3D model is 0.6 mm
- Drawing is 0.6 mm (max)
- Package height (A2):
- 3D model is 3.26 mm
- Drawing is 3.21 mm (max)
- → It seems that the 3D model of the package we have is not 100% accurate, but the difference (3.86-3.71=0.15 mm) is negligible
- Any thermal interface between the package and the cooling block should be able to "absorb" this difference
Optical transceiver
DC/DC converters
12V vs 24V (GT readout platform) vs 48V (TXI) input?
Clocks
Gliffy Diagram |
---|
displayName | clock-diagram |
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name | clock-diagram |
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pagePin | 10 |
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|
Timing
Is external electrical timing needed?
ADC/DAC
How many ADC channels are needed?
Do we need a high-speed ADC?
Temperature
NHQM103B375T10 10k NTC type thermistors are used at:
- One on carrier board going to ADC
- One on readout board going to the ADC
- One on carrier board going to external connector?
Humidity
One HIH-5031-001 sensor mounted close to the carrier connector.
LDO monitoring
ASIC monitoring
LDOs
Various peripherals
ID
A DS2411R+T&R chip is located on the readout board to provide a unique ID that can be read out by the FPGA. Another ID chip is also place on the carrier board.
Flash
Used to store the FPGA configuration.
EEPROM
Used to store operational settings and parameters.
JTAG
A 14-pin JTAG connector (Molex 87832-1420) is located at the bottom of the readout board to not interfere with the cold plate on the top.
Block diagram
Gliffy Diagram |
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displayName | 3x2-readout-board-overview |
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name | 3x2-readout-board-overview |
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pagePin | 16 |
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|
Power
- Busbars for input power or TFM connector?
Different options for power components
Gliffy Diagram |
---|
displayName | power-components-info |
---|
name | power-components-info |
---|
pagePin | 3 |
---|
|
...
Image Removed
...
FPGA
https://www.xilinx.com/products/technology/power/xpe.html
ASICs
ePixUHR Throughput Calculations
From ASIC to FPGA:
- 168*192*12(bit)*14/12(encoding) = 451584 bits/frame
- @35 kHz frame rate: 451584 bits/frame * 35 kHz = 15.8 Gbit/s per ASIC
- 15.8/8=1.975 Gbit/s per data output
- @100 kHz frame rate: 451584 bits/frame * 100 kHz = 45.2 Gbit/s per ASIC
- 45.2/8=5.65 Gbit/s per data output
Power
- ASIC Version 2 - 2023: ePixUHR-100kHz: power consumption ← Using these numbers in the table below
- ASIC Version 1 - 2022: ePixUHR: power consumption
...
Analog
...
Digital and I/O
...
Analog test system
...
Net
...
G_AS
...
G_DS
...
G_AS_2V5
...
Voltage
...
1.3 V
...
1.3V
...
2.5 V
...
Required current per ASIC
...
1.85 A ≈ 1.9 A
...
0.468 A ≈ 0.5 A
...
0.01 A
...
System requirement with 6 ASICs
(adding +30% current for PVT variation)
...
6*1.9*1.3=14.82 A
+1.3 V @ 15 A
1.3*15=19.5 W
...
6*0.5*1.3=3.9 A
+1.3 V @ 4.0 A
1.3*4=5.2 W
...
6*0.01*1.3=0.078 A
+2.5 V @ 0.5 A
2.5*0.5=1.25 W
Power block diagram
TODO
Gliffy Diagram |
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size | 300 |
---|
displayName | power-block-diagram |
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name | power-graph |
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pagePin | 10 |
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|
I/O needs
The sections below indicate how many inputs and outputs (I/Os) are needed for the main blocks of the system.
GT transceiver signals
The FPGA has two types of GT quads:
- GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
- 8 quads with 4 TX/RX in each for a total of 32 transceivers
- GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
- 11 quads with 4 TX/RX in each for a total of 44 transceivers
LEAP transceivers
The LEAP transceiver can operate up to 25 Gbit/s and therefore require GTY transceivers. There are 12 TX and 12 RX channels in total.
ASICs
There are 8 high-speed data outputs from each ASIC that can operate up to ~6 Gbit/s. For each ASIC there is also one GT clock input which the FPGA has to provide a clock to (6 Gbit/s = 3 GHz clock). In total each ASIC needs 8 RX and 1 TX channel of the FPGA. There are 6 ASICs in total.
- 6*8=48 RX channels
- 6*1=6 TX channels
...
- 451584 bits/frame * 35 kHz = 15.8 Gbit/s per ASIC
- 15.8/8=1.975 Gbit/s per data output
- @100 kHz frame rate: 451584 bits/frame * 100 kHz = 45.2 Gbit/s per ASIC
- 45.2/8=5.65 Gbit/s per data output
Power
- ASIC Version 2 - 2023: ePixUHR-100kHz: power consumption ← Using these numbers in the table below
- ASIC Version 1 - 2022: ePixUHR: power consumption
| Analog | Digital and I/O | Analog test system |
---|
Net | G_AS | G_DS | G_AS_2V5 |
---|
Voltage | 1.3 V | 1.3V | 2.5 V |
---|
Required current per ASIC | 1.85 A ≈ 1.9 A | 0.468 A ≈ 0.5 A | 0.01 A |
---|
System requirement with 6 ASICs (adding +30% current for PVT variation) | 6*1.9*1.3=14.82 A +1.3 V @ 15 A 1.3*15=19.5 W | 6*0.5*1.3=3.9 A +1.3 V @ 4.0 A 1.3*4=5.2 W | 6*0.01*1.3=0.078 A +2.5 V @ 0.5 A 2.5*0.5=1.25 W |
---|
Power block diagram
I/O needs
GT transceiver signals
- GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
- 8 quads with 4 TX/RX in each for a total of 32 transceivers
- GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
- 11 quads with 4 TX/RX in each for a total of 44 transceivers
LEAP transceivers
ASICs
- 6*8=48 RX channels
- 6*1=6 TX channels
Total data rates
- 6x ASICs, 8x data outputs per ASIC, up to 6 Gbit/s per data output: 6*8*6=288 Gbit/s
- 12x LEAP transceiver channels up to 25 Gbit/s:
- 1 channel will be used for timing?
- Data rate left: 11*25=275 Gbit/s
- 275/(6*8) ≈ 5.7 Gbit/s per ASIC in this case (+encoding)
- Running PGPv4 at 25 Gbit/s has not been proven yet!
From FPGA to PC:
- 168*192*12(bit)*66/64(PGP encoding) = 399168 bits/frame/ASIC
- @35 kHz frame rate: 6*399168*35e3 = 83.82528 Gbit/s ≈ 83.8 Gbit/s
- 83.82528/11 = 7.62048 Gbit/s ≈ 7.6 Gbit/s per LEAP channel (11 channels in total)
- @100 kHz frame rate: 6*399168*100e3 = 239.5008 Gbit/s ≈ 239.5 Gbit/s
- 239.5008/11 = 21.7728 Gbit/s ≈ 21.8 Gbit/s per LEAP channel (11 channels in total)
- 11 channels at 15 Gbit/s: 11*15*64/66(PGP encoding) = 160 Gbit/s
- 6 ASICs: 160/6*12/14(encoding) = 22.85714286 ≈ 22.9 Gbit/s per ASIC
- 22.9/8 = 2.8625 Gbit/s per data output
- 22.85714286e9/(168*192*12) = 59051.39834449 ≈ 59 kHz frame rate
GT reference clocks
- One for the LEAP channels for the GTY quads 0 to 2
- One for the ASIC clock channels for the GTY quads 4 and 5
- One for the ASIC data channels for the GTY quads 6 and 7
- One for the ASIC data channels for the GTH quads 0 to 4
- One for the ASIC data channels for the GTH quads 5 to 9
Note |
---|
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s" |
Summary
| Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 |
---|
| TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX |
---|
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP |
|
| N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C |
|
|
|
|
|
|
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Clock | |← | ← X → | →| |
| | X → | →| | | X → | →| |
|
|
|
---|
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC |
|
|
---|
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
|
---|
Useful resources
Table of contents
Components
FPGA
- Package mechanical drawing
- FPGA measured 3D model
- Difference between the drawing and 3D model used:
- Total height (A = A1 + A2):
- 3D model is 3.86 mm
- Drawing is 3.71 mm (max)
- Solder ball height (A1):
- 3D model is 0.6 mm
- Drawing is 0.6 mm (max)
- Package height (A2):
- 3D model is 3.26 mm
- Drawing is 3.21 mm (max)
- → It seems that the 3D model of the package we have is not 100% accurate, but the difference (3.86-3.71=0.15 mm) is negligible
- Any thermal interface between the package and the cooling block should be able to "absorb" this difference
Optical transceiver
DC/DC converters
Clocks
Timing
ADC/DAC
Temperature
- One on carrier board going to ADC
- One on readout board going to the ADC
- One on carrier board going to external connector?
Humidity
LDO monitoring
ASIC monitoring
LDOs
Various peripherals
ID
Flash
EEPROM
JTAG
Block diagram
Power
- Busbars for input power or TFM connector?
Different options for power components
Option A Same components as used in the GT readout platform | Option B New components with PMBUS capability |
---|
Image Added
| Gliffy Diagram |
---|
| |
---|
size | 300 |
---|
displayName | power-supply-option-b |
---|
name | power-supply-option-b |
---|
pagePin | 2 |
---|
|
|
FPGA
ASICs
ePixUHR Throughput Calculations
- 168*192*12(bit)*14/12(encoding) = 451584 bits/frame
- @35 kHz frame rate: 451584 bits/frame * 35 kHz = 15.8 Gbit/s per ASIC
- 15.8/8=1.975 Gbit/s per data output
- @100 kHz frame rate: 451584 bits/frame * 100 kHz = 45.2 Gbit/s per ASIC
- 45.2/8=5.65 Gbit/s per data output
Power
- ASIC Version 2 - 2023: ePixUHR-100kHz: power consumption ← Using these numbers in the table below
- ASIC Version 1 - 2022: ePixUHR: power consumption
| Analog | Digital and I/O | Analog test system |
---|
Net | G_AS | G_DS | G_AS_2V5 |
---|
Voltage | 1.3 V | 1.3V | 2.5 V |
---|
Required current per ASIC | 1.85 A ≈ 1.9 A | 0.468 A ≈ 0.5 A | 0.01 A |
---|
System requirement with 6 ASICs (adding +30% current for PVT variation) | 6*1.9*1.3=14.82 A +1.3 V @ 15 A 1.3*15=19.5 W | 6*0.5*1.3=3.9 A +1.3 V @ 4.0 A 1.3*4=5.2 W | 6*0.01*1.3=0.078 A +2.5 V @ 0.5 A 2.5*0.5=1.25 W |
---|
Power block diagram
I/O needs
GT transceiver signals
- GTY capable at bitrates from 0.5 Gbit/s to 32.75 Gbit/s
- 8 quads with 4 TX/RX in each for a total of 32 transceivers
- GTH capable at bitrates from 0.5 Gbit/s to 16.3 Gbit/s
- 11 quads with 4 TX/RX in each for a total of 44 transceivers
LEAP transceivers
ASICs
- 6*8=48 RX channels
- 6*1=6 TX channels
Total data rates
- 6x ASICs, 8x data outputs per ASIC, up to 6 Gbit/s per data output: 6*8*6=288 Gbit/s
- 12x LEAP transceiver channels up to 25 Gbit/s:
- 1 channel will be used for timing?
- Data rate left: 11*25=275 Gbit/s
- 275/(6*8) ≈ 5.7 Gbit/s per ASIC in this case (+encoding)
- Running PGPv4 at 25 Gbit/s has not been proven yet!
From FPGA to PC:
- 168*192*12(bit)*66/64(PGP encoding) = 399168 bits/frame/ASIC
- @35 kHz frame rate: 6*399168*35e3 = 83.82528 Gbit/s ≈ 83.8 Gbit/s
- 83.82528/11 = 7.62048 Gbit/s ≈ 7.6 Gbit/s per LEAP channel (11 channels in total)
- @100 kHz frame rate: 6*399168*100e3 = 239.5008 Gbit/s ≈ 239.5 Gbit/s
- 239.5008/11 = 21.7728 Gbit/s ≈ 21.8 Gbit/s per LEAP channel (11 channels in total)
...
- 11 channels at 15 Gbit/s: 11*15*64/66(PGP encoding) = 160 Gbit/s
- 6 ASICs: 160/6*12/14(encoding) = 22.85714286 ≈ 22.9 Gbit/s per ASIC
- 22.9/8 = 2.8625 Gbit/s per data output
- 22.85714286e9/(168*192*12) = 59051.39834449 ≈ 59 kHz frame rate
GT reference clocks
Quads can source their reference clock from a quad that is at most two quads away. This is to ensure the best jitter performance.
...
- ) = 59051.39834449 ≈ 59 kHz frame rate
GT reference clocks
- One for the LEAP channels for the GTY quads 0 to 2
- One for the ASIC clock channels for the GTY quads 4 and 5
- One for the ASIC data channels for the GTY quads 6 and 7
- One for the ASIC data channels for the GTH quads 0 to 4
- One for the ASIC data channels for the GTH quads 5 to 9
...
Note |
---|
Important note on clocking of GTY transceivers from UG578 page 48: "QPLL0 must use GTREFCLK0 and QPLL1 must use GTREFCLK1 when the channel is operating above 16.375 Gb/s" |
Summary
| Quad 0 | Quad 1 | Quad 2 | Quad 3 | Quad 4 | Quad 5 | Quad 6 | Quad 7 | Quad 8 | Quad 9 | Quad 10 |
---|
| TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX | TX | RX |
---|
GTY | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP | 4x LEAP |
|
| N/C | 4x ASIC | N/C | 4x ASIC | 3x ASIC | N/C | 3x ASIC | N/C |
|
|
|
|
|
|
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Clock | |← | ← X → | →| |
| | X → | →| | | X → | →| |
|
|
|
---|
GTH | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC | N/C | 4x ASIC |
|
|
---|
Clock | |← | - | ← X → | - | →| | |← | - | ← X → | - | →| |
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...