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The LINAC Locking project consists on synchronizing the frequencies in s10 of the two accelerators to the common denominator between the two MO, 71.4KHz, for this reason the reference clock frequency for LCLS-I was changed from 8.5MHz to 71.4KHz prior (2019) to this project. This common frequency, 71.4KHz, is 1/14th of 1MHz; allowing all the relative phases repeat.
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The 119MHz and 185.7MHz will be aligned as result of this project but the 360Hz AC sampling might not be aligned. To match the AC sampling, LCLS-II will be available thanks to use the step down chassis.
This project is taking a staged approach, first locking the RF systems then will proceed to reconfigure the TPG to get the TTL input in and use it to sample. The TPG might need a bigger FPGA to accommodate that since the 2 optical fiber inputs are used for MPS and the timing readback.
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