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PV nameDescriptionRemarks (register name)YCPSW nameAlarm Limits
<prefix>:SIMVERFirmware version number for MoFreqLocker ModuleVersion

<SIM_prefix>:M:MFL:Version:Rd


<prefix>:MODAC_RBVReadback value for DAC_OUTPUT3_REMOTE registerDAC_OUTPUT3_REMOTE<SIM_prefix>:M:MFL:DAC_OUTPUT3_REMOTE:Rd


<prefix>:MODACVOLTDAC readout in VoltSoft PV [-5...+5V]

LOLO: 1.0

LOW: 1.2

HIGH: 1.8

HIHI: 2.0

<prefix>:MODACSet value to DAC_OUTPUT3_REMOTE registerDAC_OUTPUT3_REMOTE

<SIM_prefix>:M:MFL:DAC_OUTPUT3_REMOTE:St


...

PV nameDescription RemarksAlarm Limits

<prefix>:VTUNE_VOLT

V tune voltage

ao, V
<prefix>:FREQFrequency readbackao, Hz
<prefix>:LOCK_ENABLELock enable/disablebo, 0=Enable,1=Disable

ZSV: NO_ALARM

OSV: MAJOR

<prefix>:FREQ_SETPTFrequency setpointao, Hz

TODO

LOLO:

LOW:

HIGH:

HIHI:

<prefix>:FREQ_ERRFrequency errorao, Hz

LOLO: -0.1

LOW: -0.075

HIGH: 0.075

HIHI: 0.1

<prefix>:WDOG_CNTWatchdog countlongout

...

Calculation Formula

18_17bit signed 2'comp value, so decimal value ranges +/-1.  Because this is a normalized phase value from the CORDIC:

+1 = 180degree

-1 = -180degree

Should display in degrees

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

degree = Fixed1817toFloat(u) * 180.;

Phase ShiftPhaseShiftSt

18_17bit signed 2'comp value, so decimal value ranges +/-1.  Because this is a normalized phase value from the CORDIC:

+1 = 180degree

-1 = -180degree

Should display in degrees

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

degree = Fixed1817toFloat(u) * 180.;

LOOPFILTTER_RESET value for loop filter resetLoop ResetLoopReset

18_17bit signed 2'comp value, so decimal value ranges +/-1.  Because this is a normalized phase value from the CORDIC:

+1 = 180degree

-1 = -180degree

Should display in degrees

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

degree = Fixed1817toFloat(u) * 180.;

18_17bit signed 2'comp value, so decimal value ranges +/-1.  Because this is a normalized phase value from the CORDIC:

+1 = 180degree

-1 = -180degree

Should display in degrees

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

degree = Fixed1817toFloat(u) * 180.;

<SIM_prefix>:M:PRLMST:Input_MUX:Rd

18_17 signed 2'comp registers, max value is between almost -1 and 1.  The value is normalized to 1 from the 1.8V amplitude ADC. This is amplitude, not peak to peak value

1 = 1.8V

-1 = -1.8V

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

volt = Fixed1817toFloat(u) * 1.8;

18_17 signed 2'comp registers, max value is between almost -1 and 1.  The value is normalized to 1 from the 1.8V amplitude ADC. This is amplitude, not peak to peak value

1 = 1.8V

-1 = -1.8V

/* conversion 2'scomp fixed point (18_17bit) to floating point */

#define LENGTH 18
double Fixed1817toFloat(unsigned u)

{
int u32;

u32 = (u & 1<<(LENGTH-1))? (~0x3ffff) |u : u;

return (double) u32 / (double) (0x1ffff);
}

volt = Fixed1817toFloat(u) * 1.8;

0 - loop enable

1 - loop disable:St

0 - loop enable

1 - loop disable

0 - normal operation

1 - state machine reset
PV nameDescription for PVRemarks (register name)YCPSW nameAlarm Limits
<prefix>:SIMVERFirmware version number for Lcls2 PRL Master SIMVersion

<SIM_prefix>:M:PRLMST:Version:Rd


<prefix>:PHASESHIFT_RBVreadback value for additional phase shiftPhaseShift

<SIM_prefix>:M:PRLMST:PhaseShift:Rd

<prefix>:PHASESHIFTset value for additional phase shift


<prefix>:PHASESHIFTset value for additional phase shiftPhase Shift

<SIM_prefix>:M:PRLMST:PhaseShift:St


<prefix>:LOOPFILTER_RESET_RBVreadback value for loop filter resetLoopReset<SIM_prefix>:M:PRLMST:LoopReset:Rd
<prefix>:LOOPFILTTER_RESETset value for loop filter resetLoop Reset

<SIM_prefix>:M:PRLMST:LoopReset:St


<prefix>:LEDreadback value for blue/red/green LEDLED

<SIM_prefix>:M:PRLMST:

LED:

Rd

TODO

<prefix>:PHASEERR1

phase error before the phase shifterRawPhiErr

<SIM_prefix>:M:PRLMST:RawPhiErr:Rd


<prefix>:PHASEERR2phase error after the phase shifterPhiErrFinal

<SIM_prefix>:M:PRLMST:PhiErrFinal:Rd


<prefix>:LOCKlock logic statusLockLogicState

<SIM_prefix>:M:PRLMST:LockLogicState:Rd


<prefix>:INPUTMUX_RBVreadback input muxInput MUX<prefix>:LOOPFILTER_RESET_RBVreadback value for loop filter resetLoopReset

<SIM_prefix>:M:PRLMST:

LoopReset

Input_MUX:Rd

0: for normal operation

1: Resetloopfilterintegral



<prefix>:INPUTMUXset input muxInput MUX

<SIM_prefix>:M:PRLMST:

Input_MUX:St

0: for normal operation

1: Resetloopfilterintegral


<prefix>:LEDW0SCALE_RBVreadback value for blue/red/green LEDw0 scalew0_scaleLED

<SIM_prefix>:M:PRLMST:LEDw0_scale:Rd

000: Error, FPGA image not flash, there should at least one LED on between Green and Red

001: Locked, but amplitude input is too low or high

010: Unlocked, but amplitude input is too low or high

011: Error, Locked and Unlocked should not be on in the same time

100: Error, there should at least one LED on between Green and Red

101: Locked, input amplitudes are good

110: Unlocked, input amplitudes are good

111: Error, Locked and Unlocked should not be on in the same time

<prefix>:PHASEERR1

phase error before the phase shifterRawPhiErr

<SIM_prefix>:M:PRLMST:RawPhiErr:Rd

<prefix>:PHASEERR2phase error after the phase shifterPhiErrFinal

<SIM_prefix>:M:PRLMST:PhiErrFinal:Rd

<prefix>:LOCKlock logic statusLockLogicState

<SIM_prefix>:M:PRLMST:LockLogicState:Rd

<prefix>:INPUTMUX_RBVreadback input muxInput MUX

0: Chan 1 - Chan 2

1: Chan 2 - Chan 1

<prefix>:INPUTMUXset input muxInput MUX

<SIM_prefix>:M:PRLMST:Input_MUX:St

0: Chan 1 - Chan 2

1: Chan 2 - Chan 1
<prefix>:W0SCALE_RBVreadback w0 scalew0_scale

<SIM_prefix>:M:PRLMST:w0_scale:Rd

w0 scale register.  w0 = 100Hz, this register is used to scale the w0 of the loopfilter.  Xilinx expect a 18bit signed 2's comp number with binary point at 5th bit.  Hardware register is 32bith wide, please keep value 0 after the 18th bit.
<prefix>:W0SCALEset w0 scalew0_scale

<SIM_prefix>:M:PRLMST:w0_scale:St

w0 scale register.  w0 = 100Hz, this register is used to scale the w0 of the loopfilter.  Xilinx expect a 18bit signed 2's comp number with binary point at 5th bit.  Hardware register is 32bith wide, please keep value 0 after the 18th bit.
<prefix>:W1_RBVreadback w1 value in radianw1

<SIM_prefix>:M:PRLMST:w1:Rd

w1 value in radian.  Xilinx expect a 18bit signed 2's comp number with binary point at 5th bit.  Hardware register is 32bith wide, please keep value 0 after the 18th bit.
<prefix>:W1set w1 value in radianw1

<SIM_prefix>:M:PRLMST:w1:St

w1 value in radian.  Xilinx expect a 18bit signed 2's comp number with binary point at 5th bit.  Hardware register is 32bith wide, please keep value 0 after the 18th bit.
<prefix>:PRAMPSLOPE_RBVreadback value for phase shift ramp slopePhase_ramp_gain

<SIM_prefix>:M:PRLMST:Phase_ramp_gain:Rd

Slope of the phase shift ramp function.  Internally converted to 18bit signed 2'comp value.  Entered as a decimal in the GUI
<prefix>:PRAMPSLOPEset value for phase shift ramp slopePhase_ramp_gain

<SIM_prefix>:M:PRLMST:Phase_ramp_gain:St

Slope of the phase shift ramp function.  Internally converted to 18bit signed 2'comp value.  Entered as a decimal in the GUI


<prefix>:W0SCALEset w0 scalew0_scale

<SIM_prefix>:M:PRLMST:w0_scale:St


<prefix>:W1_RBVreadback w1 value in radianw1

<SIM_prefix>:M:PRLMST:w1:Rd


<prefix>:W1set w1 value in radianw1

<SIM_prefix>:M:PRLMST:w1:St


<prefix>:PRAMPSLOPE_RBVreadback value for phase shift ramp slopePhase_ramp_gain

<SIM_prefix>:M:PRLMST:Phase_ramp_gain:Rd


<prefix>:PRAMPSLOPEset value for phase shift ramp slopePhase_ramp_gain<prefix>:ADCAMP0_RBVreadback value for ADC0 amplitude from CORDICADC0_Amp

<SIM_prefix>:M:PRLMST:ADC0_Amp:Rd

<prefix>:ADCAMP1_RBVreadback value for ADC1 amplitude from CORDICADC1_Amp

<SIM_prefix>:M:PRLMST:ADC1Phase_ramp_Ampgain:RdSt


<prefix>:ADCAMP0_RBVreadback value for ADC0 amplitude from CORDICADC0_Amp

<SIM_prefix>:M:PRLMST:ADC0_Amp:Rd

LOLO: 0.4

LOW: 0.6

HIGH: 0

HIHI: 0

<prefix>:ADCAMP1_RBVreadback value for ADC1 amplitude from CORDICADC1_Amp

<SIM_prefix>:M:PRLMST:ADC1_Amp:Rd

LOLO: 0.4

LOW: 0.6

HIGH: 0

HIHI: 0

<prefix>:LOCKDISABLE_RBVreadback value for loop lock disable setting bit in lock logic state machineLockDisable

<SIM_prefix>:M:PRLMST:LockDisable:Rd

ZSV: NO_ALARM

OSV: MAJOR

<prefix>:LOCKDISABLEset value for loop lock disableLockDisable

<SIM_prefix>:M:PRLMST:LockDisable

:St


<prefix>:LOCKRESET_RBVreadback value for reset the lock logic state machineStateReset

<SIM_prefix>:M:PRLMST:StateReset:Rd

0 - normal operation

1 - state machine reset


<prefix>:LOCKRESETset value for reset locking logicStateReset

<SIM_prefix>:M:PRLMST:StateReset:St


LED_ADCAMPL


ZSV: MINOR

OSV: NO_ALARM

LED_LOCK


ZSV: MAJOR

OSV: NO_ALARM

LED_ERROR


ZSV: NO_ALARM

OSV: MAJOR


SIM VCO (slave) PVs

<prefix> = PRL:SYS0:<NN>

...