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changes.mady.by.user Pietro King

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changes.mady.by.user Sandberg, Hampus

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  •  Check 24V to 1.8V (LT8648S) if it works at 30A
  •  Verify the power plane thickness for high-current rails (request by Doering, Dionisio)
  •  Extend analog-digital connector from 30 to 40 pin
  •  Replace LT1764 with LT3083 for simpler paralleling circuitry (see power graph)?
  •  Substitute HS DAC: from MAX5719A to AD5541A ?
  •  ASIC team is still not able to quote us on the digital section power consumption.
    •  For now I would proceed as if the requirement was double w.r.t the old version
  •  Request components for Altium library (see Altium Missing Components section)
    •  Connectors have been requested on 2023-08-28
    •  FPGA
    •  Other ICs
    •  Passives
      •  Resistors
    •  Transceiver
      •  Compare with the layout done in PADS after to make sure it's correct orientation
    • See
      Jira
      serverSLAC National Accelerator Laboratory
      serverId1b8dc293-975d-3f2d-b988-18fd9aec1546
      keyTIDIDECS-2
       
Expand
titleArchived questions
  •  Route +6V or +24V between analog and digital board?
    •  If +6V: All first-stage converters (LT8648S) must be on one the board with the input TFM connector
    •  +24V between boards
  •  For the 0.6V sink:
  •  On which board does the power connector (TFM) go and which type (TFM-112, TFM-115, etc)? (update Connectors section)
    •  TFM-113-02-L-DH was used on the ePixHR250M_2x2_Camera
    •  Analog board
  •  Use FPGA transceivers for clocking the ASICs?
    •  Yes 
    •  One per ASIC?
      •  Yes
      •  I think one per ASIC is the best solution. Is there any reason why we should go for a clock splitter?
        •  Probably no unless we run out of connector pins
  •  Does the digital board need the analog ground (AGND)? (see 100kfps DAQ support system)
    •  Will have it anyway since the TFM power connector is on the digital board
  •  What's the expected operating temperature range?
    •  -25C → +50C
  •  Are the ASIC digital supply (G_DS_X) and I/O supply (G_IO_X) shared among all four ASICs?
    •  Yes
  •  Can the DC/DC architecture be simplified? Some ICs not in stock, see DC/DC converters
    •  Replace LMZ31530 (30A) with TPSM5D1806 in parallel mode (12A) since Vcc_int is estimated at 7A?
      •  No, the 20A version should be available (LMZ31520)
  •  Provide space to measure both input (manual) and output (ADC) currents for all DC/DC?
  •  TPSM5D1806 does not work for 6V to 5.5V as a pre-LDO regulator!
    •  For 5.5V output, the minimum input voltage is 9.6V. See Table 7-3 in datasheet.
    •  Change first-stage converter to output 5.5V/5.0V instead of 6V?
      •  Second-stage LMZ31520 (Vout=0.85V) should be OK
      •  Second-stage TPSM5D1806 (Vout=1.8V and 0.9V) should be OK
      •  Changed first-stage converter to 5.0V on digital board now
  •  Remove DC/DC monitor on digital board
  •  Do we have the CML current consumption numbers?
    •  Gang is saying around 20mA (15mA + 30% LVT) per ASIC TX Transceiver (for all frequencies). ASIC RX consumption is negligible 
    •  Update power estimation table with these numbers


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