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System Power Consumption Breakdown
Board | Domain | Portion | Final Voltages | LDOs | DC/DC | DC/DC |
|---|
Analog | Analog | ASIC | G_AS_0 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | LT8648S x2 42V, 15A Synchronous Step-Down Silent Switcher 2 Max Current = 15*2 = 30A (Around 93% efficiency for 24 to 6V at max load) | ← +24 V The current drawn by the 0.6V current sink should not be counted twice since its sourced by the G_AS. The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W. If using 1.8V as the LDO input, we are burning also (1.8-1.3)V*4.4A*4 = 9W. The power drawn by the rest of analog voltages should be less than 2W. So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W. Considering the efficiency curves of the DC/DC converters: 34/85%/93% = 43W Total Analog Power | ||
G_AS_1 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | |||||||||
G_AS_2 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | |||||||
G_AS_3 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | |||||||||
G_VG_0 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ← +2.5V | LT3086 (LDO) Max 2.1A | ← +3V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (>90% efficiency for this loads) | ← +6 V | |||||
G_VG_1 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ||||||||||
G_VG_2 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ← +6 V | |||||||||
G_VG_3 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ||||||||||
G_AS_2V5 2.5V @ <0.5 A | ← +2.5V | |||||||||||
DAC/ADC/Misc. | VDD_5V | |||||||||||
+5V @ <1A? 5 W | ← 5V? | LT3086 (LDO) Max 2.1A | TODO | |||||||||
VDD_3V3 +3.3V @ <1A? 3.3 W | ← +3.3V? | LT3086 (LDO) Max 2.1A | ||||||||||
VDD_1V8 +1.8V @ <1A? 1.8 W | ← +1.8V? | LT3086 (LDO) Max 2.1A | ||||||||||
Digital | ASIC | G_DS_0 1.3V @3A | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | LT8648S x2 42V, 15A Synchronous Step-Down Silent Switcher 2 Max Current = 15*2 = 30A (Around 93% efficiency for 24 to 6V at max load) | ← +24 V For the digital consumption of the ASIC we do not have precise numbers regarding the new CML logic. Let's assume a double consumption w.r.t the LVDS design. 1.3V*6A = 8W LDO losses = 0.5*6A = 3W 11W / 85% / 93% = 14W(ASIC Digital) Worst case scenario, the remaining electronics will draw 1A, multiplied by 5.5V = 5.5W, which before the DCDC will become 5.5W /85 = 7W 42.5W Total Digital Power | |||
G_DS_X 1.3V @???A (CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | |||||||||
G_IO_0 1.3V @???A(CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | |||||||
G_IO_X 1.3V @???A(CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | |||||||||
| Digital | Digital | FPGA | VCCINT 0.85V @7.05 A 6 W | ← +0.85V | LMZ31520 DC/DC Buck converter 3V to 14.5V input 20A (Around 90% efficiency) Max 17 W_out, 19 W_in | ← +5 V Max ~60 W | LT8638S x2 42V, 10A Synchronous Step-Down Silent Switcher 2 Max Current = 10*2 = 20A (Around 93% efficiency for 24 to 5V at max load) Max 100 W_out, 110 W_in | ← +24 V Regarding the FPGA considering a worst case efficiency of the DC/DC: | ||||
VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX 1.8V @0.7A 1.3 W | ← +1.8V | TPSM5D1806 (DC/DC) 4.5V to 15V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) Max 16 W_out, 19 W_in | ||||||||||
MGTAVCC +MGTYAVCC 0.9V @3.7A 3.3 W | ← +0.9V | |||||||||||
VCC_1.2V + MGTAVTT + MGTYAVTT 1.2V @5.5A 6.6 W | ← +1.2V | TPSM5D1806 (DC/DC) 4.5V to 15V input Parallel 12A output (Between 80% and 90% efficiency) Max 15 W_out, 19 W_in | ||||||||||
DAC/ADC/Misc. | VDD_5V +5V @ <1A 5 W | |||||||||||
Is this one needed?
← 5V? | LT3086 (LDO) Max 2.1A | ← +5V | ||||
VDD_3V3 +3.3V @ <1A 3.3 W | ← +3.3V? | LT3086 (LDO) Max 2.1A | ||||
VDD_1V8 +1.8V @ <1A 1.8 W | ← +1.8V? | LT3086 (LDO) Max 2.1A | ||||
| Anchor | ||||
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