- LCLS Register-Settings
- Living Google Xcel File
- regs-20230324.py
Code Block language cpp title Firmware set values collapse true constant EPIX_CONFIG_INIT_C : EpixConfigType := ( runTriggerEnable => '0', runTriggerDelay => (others => '0'), daqTriggerEnable => '0', daqTriggerDelay => (others => '0'), acqCountReset => '0', vguardDacSetting => (others => '0'), powerEnable => (others => '0'), seqCountReset => '0', asicMask => (others => '0'), autoRunEn => '0', autoTrigPeriod => (others => '0'), autoDaqEn => '0', acqToAsicR0Delay => (others => '0'), asicR0ToAsicAcq => (others => '0'), asicAcqWidth => (others => '0'), asicAcqLToPPmatL => (others => '0'), asicRoClkT => x"0014", asicRoClkHalfT => x"00000000", asicPreAcqTime => (others => '0'), adcClkHalfT => x"00000001", totalPixelsToRead => x"000084C0", asicPins => (others => '0'), manualPinControl => (others => '0'), testPattern => '0', asicR0Width => (others => '0'), pipelineDelayA0 => (others => '0'), pipelineDelayA1 => (others => '0'), pipelineDelayA2 => (others => '0'), pipelineDelayA3 => (others => '0'), asicPpmatToReadout => (others => '0'), requestStartupCal => '0', startupAck => '0', startupFail => '0', pgpTrigEn => '0' );- TID Register-Settings (xlsx) ← Compares YML vs LCLS for ASIC & FPGA registers
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