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Table 2. Tr_bit and pixel config file combinations are required to get a specific gain mode.
Gain mode | Tr_bit value | Pixel config file |
FH | 1 | 12 |
FM | 0 | 12 |
FL | Does not matter | 8 |
AHL | 1 | 0 |
AML | 0 | 0 |
AHL-L | 1 | 4 |
AML-L | 0 | 4 |
As with the other members of the ePix family of detectors, the analog chain consists of a CSA with a switched reset scheme, a 1st order low pass filter, and a correlated double sampler. The pixel array size for the ASIC is 192x144, however, since only a small sensor is used for the prototype, only 48x48 pixels are bonded to a sensor.
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The SROdelay sets the time from the end of the ACQ window until the readout starts. Once the SRO signal goes high, the readout starts and the conversion time needed fully read out the collected values is dictated by the number of rows the ADC is reading out, and the SERDES clocking frequency used, as described here.
The additional time needed in this readout scheme to reset the channel (CSA and CDS) is yet to be experimentally determined but is currently assumed to be in the 3-4 us range.
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Table 3. Initial measurements for the FH and FM gains.
| Gain mode (median) | gain estimate |
|---|---|
| FH | 27.75 eV/ADU |
| FM | 76.15 eV/ADU |
| Ratio FM/FH | 0.364 |