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- A stand-alone RF signal can be used to simulate an input into the timing system (Clock input).
- Large discussion on timing. LLNL and LLE would like to have a lower-level timing presentation from SLAC.
- Previous timing presentation was given by Charlie, but was high-level.
- Aiming in advance of LLNL CDR (beginning of January)
- Target timeline will be week of (Tyler, feel free to adjust this date).
Tyler Johnson is working on organizing this presentation with hardware timing team.
Discussion Topics for this presentation: Event (Course) Timing (LLE/LLNL) - Overall easier and minimal hardware
- ~8 nanosecond triggers
- ~10+ picosecond jitters
- Delivered optically over fiber (TPR - Timing Pattern Receiver directly outputs trigger)
- High Precision Timing (LLNL)
- Locking laser to RF
- Custom supporting hardware
- ~1 nanosecond trigger*
- ~10 femtosecond jitter*
- *In principle, system is still in development
- Interface between timing and various systems.
- Wiring and signals required.
See resources below to links to SLAC Laser/Timing confluence pages.
Interface between laser system and timing system.
IT/Servers:
- Omar to put together an IT supported device list for Barry
- EPICS environment needs to run services such as logging system and achiever.
- SLAC may provide a rack for LLNL, but this is still being worked out.
- Half a rack dedicated to the core.
- For event timing systems, there are various small PCIE cards scattered around.
- Precision timing system is ~half rack.
- For precision timing we may need to consider optical timing as well.
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- Good read to be linked hereRead for MECU RRL Plan.
- Charlie's old confluence pages will be linked here once found.
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