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For Q6 (tested on Nov 7 2022), you can simultaneously run all 4 chips with a 1m DP cable at 640Mbps, though chip 1 will always have some failing pixels. Presumably this is a problem due to the ring (maybe one half of the data is disconnected on the flex?)
Tested positions so far
Position | Data channels on oscilloscope after turning on (no config) | Tested with YARR? |
Q4 | only data1-, data2+/- | |
Q3 | data1+/-, data2+/- | |
Q6 | data1+/-,data2+/- | All 4 chips working |
The fact that only 2 data channels show after just turning the module on seems to be normal for ITkPixV1. They correspond to the output lanes for chips 2 and 4 and might have to do with how these two chips are designated for data merging (more investigation needed).
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