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YAML file | Register name | Description |
---|---|---|
AxiVersion.yaml | UpTimeCnt | *What is this? |
BuildStamp | Time stamp of the FPGA build | |
FpgaVersion | Version | |
GitHash | Git hash of firmware project | |
AxiSysMonUltraScale.yaml | Temperature | Temperature measurement of ***WHAT*** |
AmcCarrierBsi.yaml | EthUpTime | Uptime of ***WHICH*** ethernet |
JesdRx.yaml 2 instantiations | StatusValidCnt[0] | ***WHAT*** |
StatusValidCnt[1] | ***WHAT*** | |
StatusValidCnt[2] | ***WHAT*** | |
StatusValidCnt[3] | ***WHAT*** | |
StatusValidCnt[4] | ***WHAT*** | |
StatusValidCnt[5] | ***WHAT*** | |
DaqMuxV2.yaml 2 instantiations | TriggerCascMask | covered in DaqMux documentation |
TriggerHwAutoRearm | ||
DaqMode | ||
PacketHeaderEn | ||
FreezeHwMask | ||
DecimationRateDiv | ||
DataBufferSize | ||
TrigCount | ||
DbgInputValid | ||
DbgLinkReady | ||
InputMuxSel[0/1/2/3] | ||
StreamPause[0/1/2/3] | ||
StreamReady[0/1/2/3] | ||
StreamOverflow[0/1/2/3] | ||
StreamError[0/1/2/3] | ||
InputDataValid[0/1/2/3] | ||
StreamEnabled[0/1/2/3] | ||
FrameCnt[0/1/2/3] | ||
FormatSignWidth[0/1/2/3] | ||
FormatDataWidth[0/1/2/3] | ||
FormatSign[0/1/2/3] | ||
DecimationAveraging[0/1/2/3] | ||
Timestamp[0/1] | ||
TriggerDaq | ||
ArmHwTrigger | ||
FreezeBuffers | ||
ClearTrigStatus | ||
AxiStreamDmaRingWrite.yaml 2 instantiations | Initialize | covered in waveform engine documentation |
StartAddr[0/1/2/3] | ||
EndAddr[0/1/2/3] | ||
WrAddr[0/1/2/3] | ||
Enabled[0/1/2/3] | ||
Mode[0/1/2/3] | ||
MsgDest[0/1/2/3] | ||
FramesAfterTrigger[0/1/2/3] | ||
Status[0/1/2/3] | ||
AmcCarrierCore.yaml | OutputConfig[0/1/2/3] | Crossbar configuration. Four outputs choosing from four inputs. Output and input enumeration is as follows: 0: RTM_OUT0 (NC timing) 1:FPGA (MiniTPG) 2: backplane 3:RTM_OUT1 (SC timing) |
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