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Table 2: IO port list and description

CategoryNameDirectionClock domainWidthDescription




Clock & reset logic

axiClk Input-1AXI Lite clock
axiRst InputaxiClk1AXI Lite reset
devClk_i Input-1Development clock
devRst_i InputSynced to devClk_i in DaqMux (for some reason)1Development logic reset
wfClk_i Input-
Ouput lanes' clock
wfRst_i InputwfClk_i
Output lanes' reset









DaqMux control signals and timing information

trigHw_i InputSynced to devClk_i in DaqMux1

Trigger signal to start the DaqMux streaming

  • 0 indicates no trigger event
  • 1 indicates a trigger event
trigCasc_i InputSynced to devClk_i in DaqMux1

Cascaded trigger input. Can be used along with trigHw_i when enabled in the register file

  • 0 indicates no trigger event
  • 1 indicates a trigger event
trigCasc_o OutputdevClk_i1

Output trigger signal connected to the SW Trigger Enable control register

  • 0 indicates no trigger event
  • 1 indicates a trigger event
armCasc_i InputSynced to devClk_i in DaqMux1

Cascaded trigger Arm. Arms the trigger and prepares DaqMux for trigger arrival

  • 0 indicates no arm
  • 1 indicates armed
armCasc_o Output-1

Output cascade signal connected to the Arm HW Trigger control register

  • 0 indicates no arm
  • 1 indicates armed
freezeHw_i InputSynced to devClk_i in DaqMux1

Adds invalid flag to the streams that are forwarded, and they will be discarded in one of the posterior blocks in the pipeline

  • 0 indicates valid (not freeze)
  • 1 indicates invalid (freeze)
timeStamp_i InputSynced to devClk_i in DaqMux64Time stamp coming from the AMC carrier core
bsa_i InputSynced to devClk_i in DaqMux128BSA information coming from the AMC carrier core
dmod_i InputSynced to devClk_i in DaqMux192Dmod timing information coming from the AMC carrier core












AXI Lite register memory mapped interface for reading and writing to register file

axilReadMaster InputaxiClk1

AXI Lite record containing

Read Address channel

  • araddr  : slv(31 downto 0);
  • arprot  : slv(2 downto 0);
  • arvalid : sl;

Read data channel

  • rready  : sl;
axilReadSlave OutputaxiClk1

AXI Lite record containing

 Read Address channel

  • arready : sl;

Read data channel

  • rdata   : slv(31 downto 0);
  • rresp   : slv(1 downto 0);
  • rvalid  : sl;
axilWriteMaster InputaxiClk1

AXI Lite record containing

Write address channel

  • awaddr  : slv(31 downto 0);
  • awprot  : slv(2 downto 0);
  • awvalid : sl;

Write data channel

  • wdata   : slv(31 downto 0);
  • wstrb   : slv(3 downto 0);
  • wvalid  : sl;

Write ack channel

  • bready  : sl;
axilWriteSlave OutputaxiClk1

AXI Lite record containing

Write address channel

  • awready : sl;

Write data channel

  • wready  : sl;

Write ack channel

  • bresp   : slv(1 downto 0);
  • bvalid  : sl;


Input lane array - data valid based

sampleDataArr_i InputdevClk_iN_DATA_IN_GInput data stream array of 32-bit words
sampleValidVec_i InputdevClk_iN_DATA_IN_GInput valids with each valid corresponding to the respective stream in that cycle
linkReadyVec_i InputdevClk_iN_DATA_IN_GIndicate that the stream source is ready. If is 0, the DaqMux sets the Stream Error control register to 1







Output lane array

rxAxisMasterArr_o OutputwfClk_iN_DATA_OUT_G

AXI compliant output data stream array of 32-bit words. Nonetheless, the type of rxAxisMasterArr_o is defined as follows in the AxiStreamPkg.vhd file

  • tValid : sl;
  • tData  : slv(511 downto 0);
  • tStrb  : slv(63 downto 0);
  • tKeep  : slv(63 downto 0);
  • tLast  : sl;
  • tDest  : slv(7 downto 0);
  • tId    : slv(7 downto 0);
  • tUser  : slv(63 downto 0);
rxAxisSlaveArr_i InputwfClk_iN_DATA_OUT_GAXI streams data ready signals
rxAxisCtrlArr_iInputwfClk_iN_DATA_OUT_G

AXI stream control signals as follows

  • pause    : sl;
  • overflow : sl;
  • idle     : sl;

If pause is 1, the DaqMux will not start and error is set.



Register address mappings and description

Table 3: DaqMux register address mapping and description

Register name

Address

AccessBitsAliasDescription

Control

0x0RW

0

SW Trigger Enable

Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again.

1Cascade Trigger enable

Enabling/disabling cascaded trigger

  • '0' - Disable Cascaded Trigger
  • '1' - Enable Cascaded Trigger
2Auto Rearm HW Trigger

Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger

  • '0' - Disabled (has to be armed with bit3 otherwise disabled)
  • '1' - Enabled
3Arm HW TriggerArms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register.
4Trigger Clear StatusTrigger status will be cleared (On the rising edge).
5Daq Mode

Select the data acquisition mode ( Stream stops if Error occurs )

  • '0' - Trigger mode - Normal DAQ mode
    • Has to be triggered to start every time
  • '1' - Continuous mode - The data is framed and continuously streamed out after enabled. (Still requires a trigger to start)
    • Disable the stream to stop
6Packet Header Enable

Add 128-bit header (otherwise only data will be inserted)(Applies only to Triggered mode only)

  • '0' - Disabled
  • '1' - Enabled
7SW Freeze Buffer Freezes all enabled circular buffers
8HW Freeze Buffer Enable

Enabling/disabling hardware freeze buffer request

  • '0' - Disabled
  • '1' - Enabled
Status0x1RO

0

Software Trigger Status

Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ).

1Cascade Trigger StatusCascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
2HW Trigger StatusHardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
3HW Trigger Armed StatusHardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs )
4Combined Trigger StatusCombined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] )
5Freeze Buffers Status Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] )
Decimation0x2RW15:0Decimation Rate Divisor

Sample rate divider (Decimator):

  • Averaging Enabled: (powers of two) 1,2,4,8,16,etc (max 2^12)
  • Averaging Disabled (32-bit): 1,2,3,4,etc (max 2^16-1).
  • Averaging Disabled (16-bit): 1,2,4,6,8,etc (max 2^16-1).


DataSize0x3RW
Data Buffer Size

Number of 32-bit words to forward at each trigger (if enabled header will be included in the first 14 words of data). Minimum size is 14 (the size of the header).

TimeStamp0x4RO31:0Timestamp[31:0]Timestamp [31:0] - secPastEpoch
0x5RO31:0Timestamp[63:32]Timestamp [63:32] - nsec
BSA0x6RO31:0bsa(0)

edefAvgDn

0x731:0bsa(1)edefMinor
0x831:0bsa(2)edefMajor
0x931:0bsa(3)edefInit
TrigCount0xARO31:0Trigger CountCounts valid data acquisition triggers
DbgInputValid0xBRO31:0Debug Input ValidAll DaqMux AXI input streams valid signals 
DbgLinkReady0xCRO31:0Debug Link ReadyAll DaqMux AXI input streams ready signals
InputMuxSel0x10RW4:0Input Mux Select[0]

0x1x: Stream x: Channel select Multiplexer 

0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29)

Test mode will output counter data

0x114:0Input Mux Select[1]
0x124:0Input Mux Select[2]
0x134:0Input Mux Select[3]
0x14-0x1F
Not used
DaqStatus0x20-0x23RO0Stream Pause

Debug flag: Raw diagnostic stream control pause (Waveform engine bufferDone signal. When an AXI frame is completely  written to DRAM, this bit is set)

1Stream ReadyDebug flag: Raw diagnostic stream control Ready (Waveform engine FIFO output stream ready signal)
2Stream OverflowDebug flag: Raw diagnostic stream control Overflow (set to 0 in waveform engine)
3Stream ErrorDebug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped)
4Data source readyDebug signal: The data source is ready. If not, DaqMux sets error signal to 1
5Stream EnableDebug signal: Output stream enabled
31:6Frame CountNumber of 4096 word frames sent
024-0x2F
Not used
DataFormat


0x30-0x33RW4:0Sign Bit PositionIndicating sign extension point (all bits after sign bit will be overwritten with sign)


5Data Width

Data width 32-bit or 16-bit

  • '0' : 32-bits
  • '1' : 16-bits


6Sign enable

Signed/unsigned

  • '0' : Unsigned
  • '1' : Signed


7Decimation Averaging Enable

Decimation Averaging

  • '0' : Disable
  • '1' : Enable

Functional description & block diagrams

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Trigger mode allows the user to also see a header in the beginning of each acquired packet. 



Data Header structure

  • HeaderWord[0]: dmod(31:0) - Timing pattern information
  • HeaderWord[1]: dmod(63:32) - Timing pattern information 
  • HeaderWord[2]: dmod(95:64) - Timing pattern information 
  • HeaderWord[3]: dmod(127:96) - Timing pattern information 
  • HeaderWord[4]: dmod(159:128) - Timing pattern information 
  • HeaderWord[5]: dmod(191:160) - Timing pattern information 
  • HeaderWord[6]: timeStamp_i(31:0)   –  secPastEpoch
  • HeaderWord[7]: timeStamp_i(63:32)  –  nses 
  • HeaderWord[8]: bsa(127:96) - edefAvgDn
  • HeaderWord[9]: bsa(95:64) -edefMinor
  • HeaderWord[10]: bsa(63:32) -edefMajor
  • HeaderWord[11]: bsa(31:0) -edefInit
  • HeaderWord[12]: packetSize_i
  • HeaderWord[13]: Firmware specific signals
    • [BIT31:BIT27] = "00000"
    • [BIT26:BIT26] = Trigger Header: Hardware Trigger – s_trigHw
    • [BIT25:BIT25] = Trigger Header: Cascaded Trigger – s_trigCascRe
    • [BIT24:BIT24] = Trigger Header: Software Trigger – s_trigSw
    • [BIT23:BIT23] = Data format – dec16or32_i
    • [BIT22:BIT22] = Enable decimation averaging – averaging_i
    • [BIT21:BIT21] = Test mode – test_i
    • [BIT20:BIT20] = AMC BAY Index – BAY_INDEX_G
    • [BIT19:BIT16] = Channel Index – axiNum_i
    • [BIT15:BIT00] = decimation rate divide – rateDiv_i


Clocking/performance requirements

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